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Quad/Octal Input Network Clock Generator/Synchronizer AD9548
FEATURES
Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 Hz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single differential LVDS/LVPECL output or as 2 singleended CMOS outputs Output frequencies up to 450 MHz 30-bit integer and 10-bit fractional programmable feedback divider Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz Optional low noise LC-VCO system clock multiplier Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles Software controlled power-down 88-lead LFCSP package
APPLICATIONS
Network synchronization Cleanup of reference clock jitter GPS 1 pulse per second synchronization SONET/SDH clocks up to OC-192, including FEC Stratum 2 holdover, jitter cleanup, and phase transient control Stratum 3E and Stratum 3 reference clocks Wireless base station controllers Cable infrastructure Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry. The AD9548 operates over an industrial temperature range of -40C to +85C.
FUNCTIONAL BLOCK DIAGRAM
STABLE SOURCE ANALOG FILTER
AD9548
CLOCK MULTIPLIER CLOCK DISTRIBUTION CHANNEL 0 DIVIDER CHANNEL 1 DIVIDER DIGITAL PLL REFERENCE INPUTS AND MONITOR MUX SYNC DAC CHANNEL 2 DIVIDER CHANNEL 3 DIVIDER
SERIAL CONTROL INTERFACE (SPI or I2C)
EEPROM
STATUS AND CONTROL PINS
08022-001
Figure 1.
Rev. 0
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AD9548 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Supply Voltage ............................................................................... 4 Supply Current .............................................................................. 4 Power Dissipation ......................................................................... 4 Logic Inputs (M7 to M0, RESET, TDI, TCLK, TMS) .............. 5 Logic Outputs (M7 to M0, IRQ, TDO) ..................................... 5 System Clock Inputs (SYSCLKP/SYSCLKN) ........................... 5 Distribution Clock Inputs (CLKINP/CLKINN) ...................... 6 Reference Inputs (REFA/REFAA to REFD/REFDD) .............. 7 Reference Monitors ...................................................................... 7 Reference Switchover Specifications .......................................... 8 Distribution Clock Outputs (OUT0 to OUT3) ........................ 8 DAC Output Characteristics (DACOUTP/DACOUTN) ....... 9 Time Duration of Digital Functions ........................................ 10 Digital PLL .................................................................................. 10 Digital PLL Lock Detection ...................................................... 10 Holdover Specifications ............................................................. 10 Serial Port Specifications--SPI Mode ...................................... 11 Serial Port Specifications--I C Mode ...................................... 11 Jitter Generation ......................................................................... 12 Absolute Maximum Ratings.......................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 18 Input/Output Termination Recommendations .......................... 23 Getting Started ................................................................................ 24 Power-On Reset .......................................................................... 24 Initial Pin Programming ........................................................... 24 Device Register Programming .................................................. 24 Theory of Operation ...................................................................... 26 Overview...................................................................................... 26 Reference Clock Inputs .............................................................. 27 Reference Monitors .................................................................... 27 Reference Profiles ....................................................................... 28 Reference Switchover ................................................................. 30
2
Digital PLL (DPLL) Core .......................................................... 32 Direct Digital Synthesizer ......................................................... 34 Tuning Word Processing ........................................................... 35 Loop Control State Machine ..................................................... 36 System Clock Inputs................................................................... 37 SYSCLK PLL Multiplier............................................................. 38 Clock Distribution ..................................................................... 39 Status and Control .......................................................................... 44 Multifunction Pins (M0 to M7) ............................................... 44 IRQ Pin ........................................................................................ 45 Watchdog Timer ......................................................................... 46 EEPROM ..................................................................................... 46 Serial Control Port ......................................................................... 51 SPI/I2C Port Selection................................................................ 51 SPI Serial Port Operation .......................................................... 51 I2C Serial Port Operation .......................................................... 55 I/O Programming Registers .......................................................... 58 Buffered/Active Registers .......................................................... 58 Autoclear Registers..................................................................... 58 Register Access Restrictions...................................................... 59 Register Map ................................................................................... 60 Register Map Bit Descriptions ...................................................... 70 Serial Port Configuration (Register 0000 to Register 0005) ............................................................................. 70 System Clock (Register 0100 to Register 0108) ...................... 71 General Configuration (Register 0200 to Register 0214) ..... 72 DPLL Configuration (Register 0300 to Register 031B)......... 75 Clock Distribution Output Configuration (Register 0400 to Register 0419) ............................................................................. 77 Reference Input Configuration (Register 0500 to Register 0507)............................................................................................. 81 Profile Registers (Register 0600 to Register 07FF) ................ 83 Operational Controls (Register 0A00 to Register 0A10) ...... 92 Status Readback (Register 0D00 to Register 0D19) ............... 97 Nonvolatile Memory (EEPROM) Control (Register 0E00 to Register 0E03) ........................................................................... 100 EEPROM Storage Sequence (Register 0E10 to Register 0E3F) ........................................................................... 101 Power Supply Partitions............................................................... 105 3.3 V Supplies............................................................................ 105 1.8 V Supplies............................................................................ 105
Rev. 0 | Page 2 of 112
AD9548
Thermal Performance .................................................................. 106 Calculating Digital Filter Coefficients ....................................... 107 Calculation of the Register Values ..................................... 108 Calculation of the Register Values ...................................... 108 Calculation of the Register Values .......................................109 Calculation of the Register Values .......................................109 Outline Dimensions ......................................................................110 Ordering Guide .........................................................................110
REVISION HISTORY
5/09--Revision 0: Initial Version
Rev. 0 | Page 3 of 112
AD9548 SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD = 1.8 V; TA= 25C; IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter SUPPLY VOLTAGE DVDD3 DVDD AVDD3 3.3 V Supply (Typical) 1.8 V Supply (Alternative) AVDD Min 3.135 1.71 3.135 3.135 1.71 1.71 Typ 3.30 1.80 3.30 3.30 1.80 1.80 Max 3.465 1.89 3.465 3.465 1.89 1.89 Unit V V V V V V Test Conditions/Comments Pin 7, Pin 82 Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88 Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73 Pin 31, Pin 37, Pin 38, Pin 44 Pin 31, Pin 37, Pin 38, Pin 44 Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59, Pin 63, Pin 70, Pin 74
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Table 3. The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Table 3. Table 2.
Parameter SUPPLY CURRENT IDVDD3 IDVDD IAVDD3 IAVDD3 3.3 V Supply (Typical) 1.8 V Supply (Alternative) IAVDD Min Typ 1.5 190 52 24 24 135 Max 3 215 75 110 110 163 Unit mA mA mA mA mA mA Test Conditions/Comments Pin 7, Pin 82 Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88 Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73 Pin 31, Pin 37, Pin 38, Pin 44 Pin 31, Pin 37, Pin 38, Pin 44 Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59, Pin 63, Pin 70, Pin 74
POWER DISSIPATION
Table 3.
Parameter POWER DISSIPATION Typical Configuration Min Typ 800 Max 1100 Unit mW Test Conditions/Comments fSYSCLK = 20 MHz 1 ; fS = 1 GHz 2 ; fDDS = 122.88 MHz 3 ; one LVPECL clock distribution output running at 122.88 MHz (all others powered down); one input reference running at 100 MHz (all others powered down) fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock distribution outputs configured as LVPECL at 399 MHz; all input references configured as differential at 100 MHz; fractional-N active (R = 10, S = 39, U = 9, V = 10) Conditions = typical configuration; no external pull-up or pull-down resistors
All Blocks Running
900
1400
mW
Full Power-Down
13
mW
Rev. 0 | Page 4 of 112
AD9548
Parameter Incremental Power Dissipation SYSCLK PLL Off Input Reference On Differential Single-Ended Output Distribution Driver On LVDS LVPECL CMOS
1 2
Min
Typ
Max
Unit
-105 7 13 70 75 65
mW mW mW mW mW mW
Test Conditions/Comments Conditions = typical configuration; table values show the change in power due to the indicated operation. fSYSCLK = 1 GHz1; high frequency direct input mode.
A single 3.3 V CMOS output with a 10 pF load.
fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins. fS is the sample rate of the output DAC. 3 fDDS is the output frequency of the DDS.
LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS)
Table 4.
Parameter LOGIC INPUTS (M7 to M0, RESET, TDI, TCLK, TMS) Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Input Capacitance (CIN) Min 2.1 80 3 0.8 200 Typ Max Unit V V A pF Test Conditions/Comments
LOGIC OUTPUTS (M7 TO M0, IRQ, TDO)
Table 5.
Parameter LOGIC OUTPUTS (M7 to M0, IRQ, TDO) Output High Voltage (VOH) Output Low Voltage (VOL) IRQ Leakage Current Active Low Output Mode Active High Output Mode Min 2.7 0.4 1 1 Typ Max Unit V V A A Test Conditions/Comments IOH = 1 mA IOL = 1 mA Open-drain mode VOH = 3.3 V VOL =-0 V
SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN)
Table 6.
Parameter SYSTEM CLOCK PLL BYPASSED Input Frequency Range Minimum Input Slew Rate Duty Cycle Common-Mode Voltage Differential Input Voltage Sensitivity Min 500 1000 40 1.2 100 Typ Max 1000 Unit MHz V/s % V mV p-p Test Conditions/Comments
Minimum limit imposed for jitter performance Internally generated Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input Single-ended, each pin
60
Input Capacitance Input Resistance
2 2.5
pF k
Rev. 0 | Page 5 of 112
AD9548
Parameter SYSTEM CLOCK PLL ENABLED PLL Output Frequency Range Phase-Frequency Detector (PFD) Rate Frequency Multiplication Range VCO Gain High Frequency Path Input Frequency Range Minimum Input Slew Rate Frequency Divider Range Common-Mode Voltage Differential Input Voltage Sensitivity Min 900 6 70 100.1 200 1 1 100 500 Typ Max 1000 150 255 Unit MHz MHz Assumes valid system clock and PFD rates MHz/V MHz V/s Test Conditions/Comments
8 V mV p-p
Input Capacitance Input Resistance Low Frequency Path Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity
3 2.5 3.5 50 1.2 100 100
pF k MHz V/s V mV p-p
Minimum limit imposed for jitter performance Binary steps (M = 1, 2, 4, 8) Internally generated Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input Single-ended, each pin
Input Capacitance Input Resistance Crystal Resonator Path Crystal Resonator Frequency Range Maximum Crystal Motional Resistance
3 4 10 50 100
pF k MHz
Minimum limit imposed for jitter performance Internally generated Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input Single-ended, each pin
Fundamental mode, AT cut See the System Clock Inputs section for recommendations
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Table 7.
Parameter DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN) Input Frequency Range Minimum Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity Min 62.5 75 700 100 Typ Max 500 Unit MHz V/s mV mV p-p Test Conditions/Comments
Differential Input Power Sensitivity Input Capacitance Input Resistance
-15 3 5
dBm pF k
Minimum limit imposed for jitter performance. Internally generated. Capacitive coupling required; can accommodate single-ended input by ac grounding unused input; the instantaneous voltage on either pin must not exceed the supply rails. The same as voltage sensitivity but specified as power into a 50 load. Each pin has a 2.5 k internal dcbias resistance.
Rev. 0 | Page 6 of 112
AD9548
REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD)
Table 8.
Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Minimum Input Slew Rate Common-Mode Input Voltage Differential Input Voltage Sensitivity Min Typ Max Unit Test Conditions/Comments
10 1 1 40 2 65
750 750 x 106 750 x 106
MHz Hz Hz V/s V mV
Minimum limit imposed for jitter performance Internally generated Minimum differential voltage across pins required to ensure switching between logic levels; the instantaneous voltage on either pin must not exceed the supply rails
Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low SINGLE-ENDED OPERATION Frequency Range (CMOS) Minimum Input Slew Rate Input Voltage High (VIH) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Voltage Low (VIL) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low 620 620 1 40
25 3
k pF ps ps 250 x106 Hz V/s
Minimum limit imposed for jitter performance
0.9 1.2 1.9 0.27 0.5 1.0 45 3 1.5 1.5
V V V V V V k pF ns ns
REFERENCE MONITORS
Table 9.
Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of Range Limits Validation Timer Redetect Timer
1
Min
Typ
Max
Unit
Test Conditions/Comments
1.2 9.54 x 10-7 0.001 0.001 0.1 65.535 65.535
sec f/fREF sec sec
Calculated using the nominal phase detector period (NPDP = R/fREF) 1 Programmable (lower bound subject to quality of SYSCLK) Programmable in 1 ms increments Programmable in 1 ms increments
fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
Rev. 0 | Page 7 of 112
AD9548
REFERENCE SWITCHOVER SPECIFICATIONS
Table 10.
Parameter REFERENCE SWITCHOVER SPECIFICATIONS Maximum Output Phase Perturbation (Phase Build-Out Switchover) Maximum Time/Time Slope (Hitless Switchover) Min Typ 40 315 Max 200 65,535 Unit ps ns/sec Test Conditions/Comments Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements Minimum/maximum values are programmable upper bounds; a minimum value ensures <10% error; satisfies Telcordia GR-1244-CORE requirements Calculated using the nominal phase detector period (NPDP = R/fREF) 1 Calculated using the nominal phase detector period (NPDP = R/fREF)1
Time Required to Switch to a New Reference Hitless Switchover Phase Build-Out Switchover
1
5 3
sec sec
fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DISTRIBUTION CLOCK OUTPUTS (OUT0 TO OUT3)
Table 11.
Parameter LVPECL MODE Maximum Output Frequency Rise/Fall Time (20% to 80%) Duty Cycle Differential Output Voltage Swing Common-Mode Output Voltage LVDS MODE Maximum Output Frequency Rise/Fall Time 1 (20% to 80%) Duty Cycle Differential Output Voltage Swing Balanced, VOD Unbalanced, VOD 725 200 40 247 MHz ps % mV mV Min Typ 725 180 45 630 AVDD3 - 1.5 770 AVDD3 - 1.3 Max Unit MHz ps % mV V Test Conditions/Comments Using internal current setting resistor 100 termination across output pins Magnitude of voltage across pins; output driver static Output driver static Using internal current setting resistor (nominal 3.12 k) 350 60 454 50 100 termination across the output pair
315 55 910 AVDD3 - 1.05
Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static Output driver static Voltage difference between pins; output driver static Output driver static Weak drive option not supported for operating the CMOS drivers using a 1.8 V supply 10 pF load
Offset Voltage Common-Mode, VOS Common-Mode Difference, VOS Short-Circuit Output Current CMOS MODE
1.125
1.375 50 13 24
V mV mA
Maximum Output Frequency 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply
250 25 150
MHz MHz MHz
Rev. 0 | Page 8 of 112
AD9548
Parameter Rise/Fall Time1 (20% to 80%) 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply Duty Cycle Output Voltage High (VOH) AVDD3 = 3.3 V, IOH = 10 mA AVDD3 = 3.3 V, IOH = 1 mA AVDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) AVDD3 = 3.3 V, IOL = 10 mA AVDD3 = 3.3 V, IOL = 1 mA AVDD3 = 1.8 V, IOL = 1 mA OUTPUT TIMING SKEW Between LVPECL Outputs Between LVDS Outputs Between CMOS 3.3 V Outputs Strong Drive Strength Setting Weak Drive Strength Setting Between CMOS 1.8 V Outputs Between LVPECL Outputs and LVDS Outputs Between LVPECL Outputs and CMOS Outputs ZERO-DELAY TIMING SKEW Min Typ Max Unit Test Conditions/Comments 10 pF load
0.5 8 1.5 40
2 14.5 2.5 60
ns ns ns %
10 pF load Output driver static; strong drive strength setting
2.6 2.9 1.5
V V V Output driver static; strong drive strength setting 0.3 0.1 0.1 14 13 23 24 40 14 19 5 125 138 240 V V V ps ps ps ps ps ps ps ns Output relative to active input reference; output distribution synchronization to active reference feature enabled; assumes manual phase offset compensation of deterministic latency 10 pF load Rising edge only; any divide value Rising edge only; any divide value
Weak drive not supported at 1.8 V
140
1
The listed values are for the slower edge (rise or fall).
DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)
Table 12.
Parameter DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN) Frequency Range Output Offset Voltage Min Typ Max Unit Test Conditions/Comments
62.5
450 15
MHz mV
This is the single-ended voltage at either DAC output pin (no external load) when the internal DAC code implies that no current is delivered to that pin. Single-ended, each pin has an internal 50 termination to VSS. Programmable (8 mA to 31 mA; see the DAC Output section).
Voltage Compliance Range Output Resistance Output Capacitance Full-Scale Output Current Gain Error
VSS - 0.5
0.5 50 5 20
VSS + 0.5
V pF mA
-12
+12
% FS
Rev. 0 | Page 9 of 112
AD9548
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time Min Typ 25 Max Unit ms Test Conditions/Comments Using default EEPROM storage sequence (see Register 0E10 to Register 0E3F) Using default EEPROM storage sequence (see Register 0E10 to Register 0E3F Dependent on loop-filter bandwidth
Register-to-EEPROM Upload Time
200
ms
Minimum Power-Down Exit Time Maximum Time from Assertion of the RESET pin to the M0 to M7 Pins Entering High Impedance State
10.5 45
s ns
DIGITAL PLL
Table 14.
Parameter DIGITAL PLL Phase-Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Reference Input (R) Division Factor Integer Feedback (S) Division Factor Fractional Feedback Divide Ratio
1 2
Min 1 0.001 30 1 8 0
Typ
Max 107 105 89 230 230 0.999
Unit Hz Hz Degrees
Test Conditions/Comments Maximum fPFD 1 : fS/100 2 Programmable design parameter; maximum fLOOP = fREF/(20R) 3 Programmable design parameter 1, 2, ..., 1,073,741,824 8, 9, ..., 1,073,741,824 Maximum value: 1022/1023.
fPFD is the frequency at the input to the phase-frequency detector. fS is the sample rate of the output DAC. 3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R-divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter PHASE LOCK DETECTOR Threshold Programming Range Threshold Resolution FREQUENCY LOCK DETECTOR Threshold Programming Range Threshold Resolution Min 0.001 1 0.001 1 16,700 Typ Max 65.5 Unit ns ps ns ps Reference-to-feedback period difference Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Table 16.
Parameter HOLDOVER SPECIFICATIONS Frequency Accuracy Min Typ <0.01 Max Unit ppm Test Conditions/Comments Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover
Rev. 0 | Page 10 of 112
AD9548
SERIAL PORT SPECIFICATIONS--SPI MODE
Table 17.
Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO As an Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance As an Output Output Logic 1 Voltage Output Logic 0 Voltage SDO Output Logic 1 Voltage Output Logic 0 Voltage TIMING SCLK Clock Rate, 1/tCLK Pulse Width High, tHI Pulse Width Low, tLO SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup (tS) CS to SCLK Hold (tC) CS Minimum Pulse Width High Min Typ 2.0 0.8 30 110 2 2.0 0.8 1 1 2 Max Unit V V A A pF Internal 30 k pull-down resistor V V A A pF Test Conditions/Comments Internal 30 k pull-up resistor
2.0 0.8 1 1 2 2.7 0.4 2.7 0.4
V V A A pF V V V V 1 mA load current 1 mA load current 1 mA load current 1 mA load current
40 8 12 3 0 14 10 0 6
MHz ns ns ns ns ns ns ns ns
SERIAL PORT SPECIFICATIONS--I2C MODE
Table 18.
Parameter SDA, SCL (AS INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Current Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSP Min 0.7 x DVDD3 -10 0.015 x DVDD3 0.3 x DVDD3 +10 50 Typ Max Unit V V A ns Test Conditions/Comments No internal pull-up/down resistor.
For VIN = 10% to 90% DVDD3
Rev. 0 | Page 11 of 112
AD9548
Parameter SDA (AS OUTPUT) Output Logic 0 Voltage Output Fall Time from VIHmin to VILmax TIMING SCL Clock Rate Bus-Free Time Between a Stop and Start Condition, tBUF Repeated Start Condition Setup Time, tSU; STA Repeated Hold Time Start Condition, tHD; STA Stop Condition Setup Time, tSU; STO Low Period of the SCL Clock, tLO High Period of the SCL Clock, tHI SCL/SDA Rise Time, tR SCL/SDA Fall Time, tF Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Capacitive Load for Each Bus Line, Cb1
1
Min
Typ
Max 0.4 250 400
Unit V ns kHz s s s s s s ns ns ns ns pF
Test Conditions/Comments IO = 3 mA. 10 pF Cb 400 pF.
20 + 0.1 Cb 1
1.3 0.6 0.6 0.6 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 Cb1 100 100
After this period, the first clock pulse is generated.
300 300
400
Cb is the capacitance (pF) of a single bus line.
JITTER GENERATION
Table 19.
Parameter JITTER GENERATION fREF = 1 Hz 1 ; fDDS = 122.88 MHz 2 ; fLOOP = 0.01 Hz 3 Min Typ Max Unit Test Conditions/Comments fSYSCLK = 20 MHz 4 OCXO; fS = 1 GHz 5 ; Qdivider = 1; default SysClk PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Random jitter Random jitter Random jitter Random jitter Random jitter fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5; Q-divider = 1; default SYSCLK PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Random jitter Random jitter Random jitter Random jitter Random jitter fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5; Q-divider = 1; default SYSCLK PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Random jitter Random jitter Random jitter Random jitter Random jitter
Bandwidth: 100 Hz to 61 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 8 kHz1; fDDS = 155.52 MHz2; fLOOP = 100 Hz3
0.81 0.73 0.79 0.78 0.37
ps rms ps rms ps rms ps rms ps rms
Bandwidth: 100 Hz to 77 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz fREF = 19.44 MHz1; fDDS = 155.52 MHz2; fLOOP = 1 kHz3
0.71 0.34 0.43 0.43 0.31
ps rms ps rms ps rms ps rms ps rms
Bandwidth: 100 Hz to 77 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz
1.05 0.34 0.43 0.43 0.32
ps rms ps rms ps rms ps rms ps rms
Rev. 0 | Page 12 of 112
AD9548
Parameter fREF = 19.44 Hz1; fDDS = 311.04 MHz2; fLOOP = 1 kHz3 Min Typ Max Unit Test Conditions/Comments fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5; Q-divider = 1; default SYSCLK PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types Random jitter Random jitter Random jitter Random jitter Random jitter
Bandwidth: 100 Hz to 100 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz
1 2
0.67 0.31 0.33 0.33 0.16
ps rms ps rms ps rms ps rms ps rms
fREF is the frequency of the active reference. fDDS is the output frequency of the DDS. 3 fLOOP is the DPLL digital loop filter bandwidth. 4 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins. 5 fS is the sample rate of the output DAC.
Rev. 0 | Page 13 of 112
AD9548 ABSOLUTE MAXIMUM RATINGS
Table 20.
Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) DAC Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2V 3.6 V 3.6 V -0.5 V to DVDD3 + 0.5 V -65C to +150C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 14 of 112
AD9548 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DVDD M7 M6 M5 M4 DVDD DVDD3 M3 M2 M1 M0 DVDD IRQ NC AVDD AVDD3 REFDD REFD AVDD REFCC REFC AVDD3
DVDD SCLK/SCL SDIO SDO CS/SDA DVDD DVDD3 TCLK TMS TDO TDI DVDD RESET DVDD DVDD NC VSS DACOUTP DACOUTN VSS AVDD3 AVDD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AD9548
TOP VIEW (Not to Scale) 88-LEAD LFCSP 12mm x 12mm 0.5mm PITCH
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
AVDD3 REFBB REFB AVDD REFAA REFA AVDD3 AVDD TDC_VRT TDC_VRB NC AVDD VSS SYSCLKP SYSCLKN VSS AVDD SYSCLK_LF SYSCLK_VREG AVDD3 NC NC
AVDD AVDD VSS CLKINN CLKINP VSS AVDD OUT_RSET AVDD3 OUT0P OUT0N AVDD OUT1P OUT1N AVDD3 AVDD3 OUT2P OUT2N AVDD OUT3P OUT3N AVDD3
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
Figure 2. 88-Lead LFCSP Pin Configuration
Table 21. Pin Function Descriptions
Pin No. 1, 6, 12, 77, 83, 88 2 3 Mnemonic DVDD SCLK/SCL SDIO Input/ Output I I I/O Pin Type Power 3.3 V CMOS 3.3 V CMOS Description 1.8 V Digital Supply. Serial Programming Clock. Data clock for serial programming. Serial Data Input/Output. When the device is in 4-wire mode, data is written via this pin. In 3-wire mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin. Chip Select (SPI). Active low. When programming a device, this pin must be held low. In systems where more than one AD9548 is present, this pin enables individual programming of each AD9548 (in I2C(R) mode, this is a serial data pin). This pin has an internal 10 k pull-up resistor but only in SPI mode. 3.3 V I/O Digital Supply. JTAG Clock. Internal pull-down resistor; no connection if JTAG is not used. JTAG Mode. Internal pull-up resistor; no connection if JTAG is not used. JTAG Output. No connection if JTAG is not used JTAG Input. Internal pull-up resistor; no connection if JTAG is not used. Chip Reset. When this active high pin is asserted, the chip goes into reset. This pin has an internal 50 k pull-down resistor. 1.8 V DAC Decode Digital Supply. Keep isolated from the 1.8 V core digital supply. No Connect. Analog Ground. Connect to ground. DAC Output. DACOUTP contains an internal 50 pull-down resistor. Complementary DAC Output. DACOUTN contains an internal 50 pull-down resistor. 3.3 V Analog (DAC) Power Supply.
Rev. 0 | Page 15 of 112
4 5
SDO CS/SDA
O I
3.3 V CMOS 3.3 V CMOS
7, 82 8 9 10 11 13 14, 15 16, 45, 46 17, 20, 25, 28, 51, 54 18 19 21, 22
DVDD3 TCLK TMS TDO TDI RESET DVDD NC VSS DACOUTP DACOUTN AVDD3
I I I O I I I O O O I
Power
3.3 V CMOS Power Ground Differential output Differential output Power
08022-002
AD9548
Pin No. 23, 24 26 Mnemonic AVDD CLKINN Input/ Output I I Pin Type Power Differential input Description 1.8 V Analog (DAC) Power Supply. Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTN output. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal whose single-ended swing is at least 400 mV. Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTP output 1.8 V Analog (Input Receiver) Power Supply. Connect an optional 3.12 k resistor from this pin to ground (see the Output Current Control with an External Resistor section). Analog Supply for Output Driver. These pins are normally 3.3 V but can be 1.8 V. Pin 31 powers Out0x. Pin 37 powers OUT1x. Pin 38 powers OUT2x. Pin 44 powers OUT3x. Apply power to these pins even if the corresponding outputs (OUT0P/ OUT0N, OUT1P/ OUT1N, OUT2P/ OUT2N, and OUT3P/ OUT3N) are not used. See the Power Supply Partitions section. Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. Complementary Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS. 1.8 V Analog (Output Divider) Power Supply. Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. Complementary Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS. Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. Complementary Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS. Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. Complementary Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS. 3.3 V Analog (System Clock) Power Supply. System Clock Loop Filter Voltage Regulator. Connect a 0.1 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated SYSCLK PLL multiplier's external loop filter (see the SYSCLK PLL Multiplier section). System Clock Multiplier Loop Filter. When using the frequency multiplier to drive the system clock, an external loop filter can be attached to this pin. 1.8 V Analog (System Clock) Power Supply. Complementary System Clock Input. Complementary signal to SYSCLKP. SYSCLKN contains internal dc biasing and should be ac-coupled with a 0.01 F capacitor, except when using a crystal, in which case connect the crystal across SYSCLKP and SYSCLKN.
27 29 30 31, 37, 38, 44
CLKINP AVDD OUT_RSET AVDD3
I I O I
Differential input Power Current set resistor Power
32
OUT0P
O
LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS Power LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS LVPECL, LVDS, or CMOS Power
33
OUT0N
O
34, 41 35
AVDD OUT1P
I O
36
OUT1N
O
39
OUT2P
O
40
OUT2N
O
42
OUT3P
O
43
OUT3N
O
47 48
AVDD3 SYSCLK_VREG
I I
49 50, 55 52
SYSCLK_LF AVDD SYSCLKN
O I I Power Differential input
Rev. 0 | Page 16 of 112
AD9548
Pin No. 53 Mnemonic SYSCLKP Input/ Output I Pin Type Differential input Description System Clock Input. SYSCLKP contains internal dc biasing and should be accoupled with a 0.01 F capacitor, except when using a crystal, in which case connect the crystal across SYSCLKP and SYSCLKN. Single-ended 1.8 V CMOS is also an option but can introduce a spur if the duty cycle is not 50%. When using SYSCLKP as a single-ended input, connect a 0.01 F capacitor from SYSCLKN to ground. No Connection. These pins should be left floating. 1.8 V Analog Power Supply. Use capacitive decoupling on these pins (see Figure 38). 3.3 V Analog (Reference Input) Power Supply. Reference A Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS. Complementary Reference A Input. Complementary signal to the input provided on Pin 61. The user can configure this pin as a separate single-ended input. 1.8 V Analog (Reference Input) Power Supply. Reference B Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS. Complementary Reference B Input. Complementary signal to the input provided on Pin 64. The user can configure this pin as a separate single-ended input. Reference C Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS. Complementary Reference C Input. Complementary signal to the input provided on Pin 68. The user can configure this pin as a separate single-ended input. Reference D Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS. Complementary Reference D Input. Complementary signal to the input provided on Pin 71. The user can configure this pin as a separate single-ended input. Interrupt Request Line. Configurable I/O Pins. These pins are configured under program control.
56, 75 59 57, 58 60, 66, 67, 73 61
NC AVDD TDC_VRB, TDC_VRT AVDD3 REFA
I I I I I
Power
Power Differential input Differential input Power Differential input Differential input Differential input Differential input Differential input Differential input Logic 3.3 V CMOS
62 63, 70, 74 64
REFAA AVDD REFB
I I I
65 68
REFBB REFC
I I
69 71
REFCC REFD
I I
72 76 78, 79, 80, 81, 84, 85, 86, 87 EP
REFDD IRQ M0, M1, M2, M3, M4, M5, M6, M7 VSS
I O I/O
O
Exposed pad
The exposed pad must be connected to ground (VSS).
Rev. 0 | Page 17 of 112
AD9548 TYPICAL PERFORMANCE CHARACTERISTICS
fR = input reference clock frequency; fO = clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency; LBW = DPLL loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; ICP = SYSCLK PLL charge pump current; LF = SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless otherwise noted.
-70 -80 -90 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 173fs (-75.4dBc) 20kHz TO 80MHz: 315fs (-70.2dBc) (EXTRAPOLATED) -70 -80 -90 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 103fs (-74.0dBc) 20kHz TO 80MHz: 160fs (-70.1dBc)
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150
08022-068
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150
08022-066 08022-067
-160 100
1k
10k
100k
1M
10M
100M
-160 100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 3. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 155.52 MHz, LBW = 1 kHz, fSYS = 1 GHz, PLL Off
-70 -80 -90
PHASE NOISE (dBc/Hz)
Figure 5. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 311.04 MHz, LBW = 1 kHz, fSYS = 1 GHz, PLL Off
-70 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 310fs (-64.4dBc) 20kHz TO 80MHz: 330fs (-63.9dBc)
INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 333fs (-69.8dBc) 20kHz TO 80MHz: 430fs (-67.6dBc) (EXTRAPOLATED)
-80 -90
PHASE NOISE (dBc/Hz)
08022-056
-100 -110 -120 -130 -140 -150 -160 100
-100 -110 -120 -130 -140 -150 -160 100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 4. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 155.52 MHz, LBW = 1 kHz, fSYS = 50 MHz (Crystal), PLL On
Figure 6. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 311.04 MHz, LBW = 1 kHz, fSYS = 50 MHz (Crystal), PLL On
Rev. 0 | Page 18 of 112
AD9548
-70 -80 -90
PHASE NOISE (dBc/Hz)
INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (-69.0dBc) 20kHz TO 80MHz: 441fs (-67.3dBc) (EXTRAPOLATED)
-70 -80
50MHz CRYSTAL
-90
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150
08022-069
-100 -110 -120 -130 -140 -150
ROHDE & SCHWARZ SMA100 (1GHz) 1k 10k 100k 1M 10M 100M
08022-058 08022-051 08022-054
ROHDE & SCHWARZ SMA100 (50MHz)
-160 100
1k
10k
100k
1M
10M
100M
-160 100
FREQUENCY OFFSET (Hz)
FREQUENCY (Hz)
Figure 7. Additive Phase Noise (Output Driver = LVPECL), fR = 19.44 MHz, fO = 155.52 MHz, LBW = 1 kHz, fSYS = 50 MHz, PLL On
-70 -80 -90
PHASE NOISE (dBc/Hz)
Figure 10. Additive Phase Noise Comparison of SYSCLK Input Options (Output Driver = LVPECL), fR = 19.44 MHz, fO = 311.04 MHz, LBW = 1 kHz
-70 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 356fs (-69.2dBc) 20kHz TO 80MHz: 435fs (-67.4dBc) (EXTRAPOLATED)
INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 10MHz: 717fs (-65.1dBc) 12kHz TO 20MHz: 725fs (-65.0dBc) 20kHz TO 80MHz: 790fs (-64.3dBc)
PHASE NOISE (dBc/Hz)
-80 -90 -100 -110 -120 -130 -140 -150
08022-044
-100 -110 -120 -130 -140 -150 -160 10
100
1k
10k
100k
1M
10M
100M
-160 100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 8. Additive Phase Noise (Output Driver = LVPECL), fR = 1 Hz, fO = 122.88 MHz, LBW = 0.05 Hz, fSYS = 20 MHz (OCXO), PLL On
-70 -80 -90 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 336fs (-69.7dBc) 20kHz TO 80MHz: 425fs (-67.6dBc) (EXTRAPOLATED)
Figure 11. Additive Phase Noise (Output Driver = LVPECL), fR = 1 Hz, fO = 155.52 MHz, LBW = 0.05 Hz, fSYS = 50 MHz, PLL On
-70 -80 -90
PHASE NOISE (dBc/Hz)
INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 245fs (-72.4dBc) 20kHz TO 80MHz: 300fs (-64.3dBc) (EXTRAPOLATED)
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150
08022-052
-100 -110 -120 -130 -140 -150 -160 100
-160 100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 9. Additive Phase Noise (Output Driver = LVPECL), fR = 8 kHz, fO = 155.52 MHz, LBW = 100 Hz, fSYS = 50 MHz (Crystal), PLL On
Figure 12. Additive Phase Noise (Output Driver = LVPECL) , fR = 19.44 MHz, fO = 155.52 MHz, LBW = 1 kHz, fSYS = 50 MHz (Crystal), PLL On with 2x Frequency Multiplier, ICP = 375 A, LF = External (350 kHz)
Rev. 0 | Page 19 of 112
AD9548
-90 -100
CLOSED-LOOP GAIN (dB)
10
CLOSED-LOOP PEAKING: 0.04dB
0 -10 -20 -30 -40 -50 -60 ROHDE & SCHWARZ SMA100 (50MHz) 1k 10k 100k 1M 10M
08022-053
PHASE NOISE (dBc/Hz)
-110 -120 -130 -140 -150 -160 -170 100 20MHz OCXO ROHDE & SCHWARZ SMA100 (1GHz)
100
1k FREQUENCY OFFSET (Hz)
10k
100k
FREQUENCY OFFSET (Hz)
Figure 13. Phase Noise of SYSCLK Input Sources
Figure 16. Jitter Transfer Bandwidth, Output Driver = LVPECL, fR = 19.44 MHz, fO = 155.52 MHz, LBW = 100 Hz (Phase Margin = 88), fSYS = 1 GHz, PLL Off
2.0
1.0
0.8 LVPECL
AMPLITUDE (V) 1.5 20pF LOAD
5pF LOAD
0.6
0.4 LVDS 0.2
AMPLITUDE (V)
1.0 10pF LOAD
08022-049
0
100
200
300
400
500
600
700
0
50
100
150
200
250
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Amplitude vs. Toggle Rate, LVPECL and LVDS
4.0
4.0
Figure 17. Amplitude vs. Toggle Rate, 1.8 V CMOS
3.5 10pF LOAD
AMPLITUDE (V) AMPLITUDE (V)
3.5 5pF LOAD 3.0 10pF LOAD 2.5
3.0
2.5 20pF LOAD 2.0
2.0
1.5
1.5
08022-055
0
100
200
300
400
500
0
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Amplitude vs. Toggle Rate, 3.3 V CMOS (Strong Mode)
Figure 18. Amplitude vs. Toggle Rate, 3.3 V CMOS (Weak Mode)
Rev. 0 | Page 20 of 112
08022-063
1.0
1.0
08022-062
0
0.5
08022-047
-70 10
AD9548
140 130
40
20pF LOAD
120 110 LVPECL
35 10pF LOAD POWER (mW) 30 5pF LOAD
POWER (mW)
100 90 80 70 60
08022-064
25
LVDS
20
0
100
200
300
400
500
0
50
100
FREQUENCY (MHz)
150
200
FREQUENCY (MHz)
Figure 19. Power Consumption vs. Frequency, LVPECL and LVDS (Single Channel)
160 140 120
Figure 22. Power Consumption vs. Frequency, 1.8 V CMOS
34 32 30
POWER (mW)
100 10pF LOAD 80 60 40 20 0 50 100 150 200 250 300 350 FREQUENCY (MHz) 5pF LOAD
POWER (mW)
20pF LOAD
10pF LOAD 28 20pF LOAD 26 5pF LOAD
24 22 20 10
08022-060
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 20. Power Consumption vs. Frequency, 3.3 V CMOS (Strong Mode)
1.0 0.8
0.5 0.4
Figure 23. Power Consumption vs. Frequency, 3.3 V CMOS (Weak Mode)
DIFFERENTIAL AMPLITUDE (V)
DIFFERENTIAL AMPLITUDE (V)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
08022-050
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 1 2 TIME (ns) 3 4 5
08022-048
-1.0
0 1 2 TIME (ns) 3 4 5
-0.5
Figure 21. Output Waveform, LVPECL (400 MHz)
Figure 24. Output Waveform, LVDS (400 MHz)
Rev. 0 | Page 21 of 112
08022-059
08022-061
50
15
AD9548
3.5 10pF LOAD 3.0 20pF LOAD 2.5
3.5 5pF LOAD 3.0 2.5
AMPLITUDE (V)
AMPLITUDE (V)
2.0 1.5 1.0 0.5 0 -0.5 0 2 4 6 8 TIME (ns) 10 12 14 16
2.0 1.5 1.0 0.5 0 -0.5 0
20 pF LOAD
08022-057
10
20
30
40 TIME (ns)
50
60
70
80
Figure 25. Output Waveform, 3.3 V CMOS (100 MHz, Strong Mode)
2.0 10pF LOAD 1.5 20pF LOAD
Figure 27. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode)
AMPLITUDE (V)
1.0
0.5
0
0
2
4
6
8 TIME (ns)
10
12
14
16
Figure 26. Output Waveform, 1.8 V CMOS (100 MHz)
08022-065
-0.5
Rev. 0 | Page 22 of 112
08022-046
AD9548 INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.1F 0.1F
(OPTIONAL)
AD9548
3.3V LVDS OUTPUT
HIGH IMPEDANCE INPUT 0.1F
100
DOWNSTREAM DEVICE 0.1F
08022-003
100
AD9548
SELF-BIASED SYSCLK INPUT
08022-006
Figure 28. AC-Coupled LVDS or LVPECL Output Driver
Figure 31. SYSCLKx Input
0.1F
AD9548
100
(OPTIONAL)
08022-004
Figure 29. DC-Coupled LVDS or LVPECL Output Driver
0.1F
(OPTIONAL)
Figure 32. CLKINx Input
AD9548
SELF-BIASED REFERENCE INPUT
08022-005
0.1F
Figure 30. Reference Input
100
Rev. 0 | Page 23 of 112
08022-007
3.3V LVPECLCOMPATIBLE OUTPUT
100
DOWNSTREAM DEVICE
0.1F
AD9548
SELF-BIASED CLKINx INPUT
AD9548 GETTING STARTED
POWER-ON RESET
The AD9548 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V 0.1 V and DVDD (Pin 1, Pin 6, Pin 12, Pin 77, Pin 83, and Pin 88) is greater than 1.4 V 0.05 V, the device generates a 75 ns reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. Within 45 ns after the leading edge of the internal reset pulse, the M0 to M7 multifunction pins behave as high impedance digital inputs and remain so until programmed otherwise. It is essential to program the system clock period because many of the AD9548 subsystems rely on this value. It is highly recommended to program the system clock stability timer, as well. This is especially important when using the system clock PLL but also applies if using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the AD9548.
Initialize the System Clock
After the system clock functionality is programmed, issue an I/O update using Register 0005, Bit 0 to invoke the system clock settings.
INITIAL PIN PROGRAMMING
During a device reset (either via the power-up reset pulse or the RESET pin), the multifunction pins (M0 to M7) behave as high impedance inputs, but upon removal of the reset condition, level-sensitive latches capture the logic pattern present on the multifunction pins. The AD9548 requires that the user supply the desired logic state to the M0 to M7 pins by means of pull-up and/or pull-down resistors (nominally 10 k to 30 k). The initial state of the M0 to M7 pins following a reset is referred to as FncInit, Bits[7:0]. Bits[7:0] of FncInit map directly to the logic states of M7:0, respectively. The three LSBs of FncInit (FncInit, Bits[2:0]) determine whether the serial port interface behaves according to the SPI or I2C protocol. Specifically, FncInit, Bits[2:0] = 000 selects the SPI interface, while any other value selects the I2C port with the three LSBs of the I2C bus address set to the value of FncInit, Bits[2:0]. The five MSBs of FncInit (FncInit, Bits[7:3]) determine the operation of the EEPROM loader. On the falling edge of RESET, if FncInit, Bits[7:3] = 00000, then the EEPROM contents are not transferred to the control registers and the device registers assume their default values. However, if FncInit, Bits[7:3] 00000, then the EEPROM controller transfers the contents of the EEPROM to the control registers with condition = FncInit, Bits[7:3] (see the EEPROM section).
Calibrate the System Clock (Only if Using SYSCLK PLL)
Set the calibrate system clock bit in the sync/cal register (Address 0A02, Bit 0) and issue an I/O update. Then clear the calibrate system clock bit and issue another I/O update. This action allows time for the calibration to proceed while programming the remaining device registers.
Program the Multifunction Pins (Optional)
This step is required only if the user intends to use any of the multifunction pins for status or control. The multifunction pin parameters resides in the 0200 to 0207 register address space. The default configuration of the multifunction pins is as an undesignated high impedance input pin.
Program the IRQ Functionality (Optional)
This step is required only if the user intends to use the IRQ feature. IRQ control resides in the 0200 to 0207 register address space. It includes the following: * * IRQ pin mode control IRQ mask
The IRQ mask default values prevent interrupts from being generated. The IRQ pin mode default is open-drain NMOS.
Program the Watchdog Timer (Optional)
This step is required only if the user intends to use it. Watchdog timer control resides in the 0200 register address space. The watchdog timer is disabled by default.
DEVICE REGISTER PROGRAMMING
The initial state of the M0 to M7 pins establishes the serial I/O port protocol (SPI or I2C). Using the appropriate serial port protocol, and assuming that an EEPROM download is not used, program the device according to the recommended sequence described in the Program the System Clock Functionality section through the Generate the Output Clock section.
Program the DAC Full-Scale Current (Optional)
This step is required only if the user intends to use a full-scale current setting other than the default value. DAC full-scale current control resides in the 0200 register address space.
Program the Digital Phase-Locked Loop (DPLL)
The DPLL parameters reside in the 0300 register address space. They include the following: * * * * * Free-run frequency (DDS frequency tuning word) DDS phase offset DPLL pull-in range limits DPLL closed-loop phase offset Phase slew control (for hitless reference switching)
Program the System Clock Functionality
The system clock parameters reside in the 0100 register address space. They include the following: * * * System clock PLL controls System clock period System clock stability timer
Rev. 0 | Page 24 of 112
AD9548
* Tuning word history control (for holdover operation)
Program the Clock Distribution Outputs
The clock distribution parameters reside in the 0400 register address space. They include the following: * * * * * Output power-down control Output enable (disabled by default) Output synchronization Output mode control Output divider functionality
* * *
Reference prescaler (R-divider) Feedback dividers (S, U, and V) Phase and frequency lock detector controls
Generate the Reference Acquisition
After the registers are programmed, issue an I/O update using Register 0005, Bit 0 to invoke all of the register settings programmed up to this point. If the settings are programmed for manual profile assignment, the DPLL locks to the first available reference that has the highest priority. If the settings are programmed for automatic profile assignment, then write to the reference profile detect register (Address 0A0D) to select the state machines that require starting. Next, issue an I/O update (Address 0005, Bit 0) to start the selected state machines. Upon completion of the reference detection sequence, the DPLL locks to the first available reference with the highest priority.
Program the Reference Inputs
The reference input parameters reside in the 0500 register address space. They include the following: * * * * Reference power-down Reference logic family Reference profile assignment control Phase build-out control
Generate the Output Clock
If the registers are programmed for automatic clock distribution synchronization via DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs (assuming the output is enabled and that the DDS output signal has been routed to the CLKIN input pins). Otherwise, set and then clear the sync distribution bit (Address 0A02, Bit 1) or use a multifunction pin input (if programmed accordingly) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs.
Program the Reference Profiles
The reference profile parameters reside in the 0600 to 0700 register address space. They include the following: * * * * * * Reference priority Reference period Reference period tolerance Reference validation timer Reference redetect timer Digital loop-filter coefficients
Rev. 0 | Page 25 of 112
AD9548 THEORY OF OPERATION
AD9548
POST DIV OUT_RSET OUT0P OUT0N OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N CLKINP
REFA REFAA REFB REFBB REFC REFCC REFD REFDD
DIFFERENTIAL OR SINGLE-ENDED
POST DIV POST DIV
DIGITAL PLL CORE /S PROG. DIGITAL LOOP FILTER
POST DIV
4 OR 8
TDC/PFD /R
TW CLAMP AND HISTORY
DDS/DAC
CLKINN CLOCK DISTRIBUTION EXTERNAL ANALOG FILTER
PHASE CONTROLLER
HOLDOVER LOGIC
INPUT REF MONITOR
LOW NOISE CLOCK MULTIPLIER CONTROL LOGIC
SYSCLK PORT
08022-009
M0 TO M7 IRQ
IRQ AND STATUS LOGIC
AMP
DIGITAL INTERFACE
SYSCLKN SYSCLKP
Figure 33. Detailed Block Diagram
OVERVIEW
The AD9548 provides clocking outputs directly related in phase and frequency to the selected (active) reference but with jitter characteristics primarily governed by the system clock. The AD9548 supports up to eight reference inputs and a wide range of reference frequencies. The core of this product is a digital phase-locked loop (DPLL). The DPLL has a programmable digital loop filter that greatly reduces jitter transferred from the active reference to the output. The AD9548 supports both manual and automatic holdover. While in holdover, the AD9548 continues to provide an output as long as the DAC sample clock is present. The holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition. The device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. A direct digital synthesizer (DDS) and integrated DAC constitute a digitally controlled oscillator (DCO). The DCO output is a sinusoidal signal (450 MHz maximum) at a frequency determined by the active reference frequency and the programmed values of the reference prescaler (R) and feedback divider (S). Although not explicitly shown in Figure 33, the S-divider has both an integer and fractional component, which is similar to a fractional-N synthesizer.
The SYSCLKx input provides the sample clock for the DAC, which is either a directly applied high frequency source or a low frequency source coupled with the integrated PLL-based frequency multiplier. The low frequency option also allows for the use of a crystal resonator connected directly across the SYSCLKx inputs. The DAC output routes directly off-chip, where an external filter removes the sampling artifacts before returning the signal on-chip at the CLKINx inputs. Once on-chip, an integrated comparator converts the filtered sinusoidal signal to a clock signal (square wave) with very fast rise and fall times. The clock distribution section provides four output drivers. Each driver is programmable either as a single differential LVPECL/LVDS output or as a dual single-ended CMOS output. Furthermore, each of the four outputs has a dedicated 30-bit programmable postdivider. The clock distribution section operates at up to 725 MHz. This enables use of a band-pass reconstruction filter (for example, a SAW filter) to extract a Nyquist image from the DAC output spectrum, thereby allowing output frequencies that exceed the typical 450 MHz limit at the DAC output.
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AD9548
REFERENCE CLOCK INPUTS
Four pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate spontaneously. When configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. The receiver is internally dc biased in order to handle ac-coupled operation. When configured for single-ended operation, the input receivers exhibit a pull-down load of 45 k (typical). Three user-programmable threshold voltage ranges are available for each single-ended receiver. previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as nonfaulted. The outer tolerance applies to an already nonfaulted reference. It specifies the largest period tolerance that a nonfaulted reference can exhibit before being faulted. To produce decision hysteresis, the inner tolerance must be less than the outer tolerance. That is, a faulted reference must meet tighter requirements to become nonfaulted than a nonfaulted reference must meet to become faulted.
Reference Validation Timer
Each reference input has a dedicated validation timer. The validation timer establishes the amount of time that a previously faulted reference must remain fault free before the AD9548 declares it nonfaulted. The timeout period of the validation timer is programmable via a 16-bit register (see the validation register contained within each of the eight profile registers in the register map, Address 0600 to Address 07FF). The 16-bit number stored in the validation register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms. Note that a validation period of 0 must be programmed to disable the validation timer. With the validation timer disabled, the user must validate a reference manually via the force validation timeout register (Address 0A0E).
REFERENCE MONITORS
The reference monitors depend on a known and accurate system clock period. Therefore, the functioning of the reference monitors is not reliable until the system clock is stable. To avoid an incorrect valid indication, the reference monitors indicate fault status until the system clock stability timer expires (see the System Clock Stability Timer section).
Reference Period Monitor
Each reference input has a dedicated monitor that repeatedly measures the reference period. The AD9548 uses the reference period measurements to determine the validity of the reference based on a set of user provided parameters in the profile register area of the register map (see the Profile Registers (Register 0600 to Register 07FF) section). The AD9548 also uses the reference period monitor to assign a particular reference to a profile when the user programs the device for automatic profile assignment. The monitor works by comparing the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. The parameters include the reference period, an inner tolerance, and an outer tolerance. A 50-bit number defines the reference period in units of femtoseconds. The 50-bit range allows for a reference period entry of up to 1.125 sec. However, an actual reference signal with a period in excess of 1 sec is beyond the recommended operating range of the device. A 20-bit number defines the inner and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20). The use of two tolerance values provides hysteresis for the monitor decision logic. The inner tolerance applies to a
Reference Redetect Timer
Each reference input has a dedicated redetect timer. The redetect timer is useful only with the device programmed for automatic profile selection. The redetect timer establishes the amount of time that a reference must remain faulted before the AD9548 attempts to reassign it to a new profile. The timeout period of the redetect timer is programmable via a 16-bit register (see the redetect timeout register contained within each of the eight profile registers in the register map, Address 0600 to Address 07FF). The 16-bit number stored in the redetect timeout register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms. Note that a timeout period of 0 must be programmed to disable the redetect timer.
Reference Validation Override Control
Register 0A0E to Register 0A10 provide the user with the ability to override the reference validation logic enabling a certain level of troubleshooting capability. Each of the eight input references has a dedicated block of validation logic as shown in Figure 34. The state of the valid signal at the output is what defines a particular reference as valid (1) or not (0), which includes the validation period (if activated) as prescribed by the validation timer. The override controls are the three control bits on the left side of the diagram.
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AD9548
REGISTER CONTROL BITS FORCE VALIDATION TIMEOUT VALIDATION TIMER REF MONITOR BYPASS REF MONITOR OVERRIDE 1 0 REFERENCE MONITOR REF FAULT
08022-010
REFERENCE VALIDATION LOGIC (8 COPIES, 1 PER REFERENCE INPUT) DQ VALID
R
R FAULTED
EN
TIMEOUT
Figure 34. Reference Validation Override
The main feature to note is that any time faulted = 1, the output latch is reset, which forces valid = 0 (indicating an invalid reference) regardless of the state of any other signal. Under the default condition (that is, all three control bits are 0), the reference monitor is the primary source of the validation process. This is because, under the default condition, the ref fault signal from the reference monitor is identically equal to the faulted signal. The function of the faulted signal is fourfold. * Any time faulted = 1, then valid = 0, regardless of the state of any other control signal. Therefore, faulted = 1 indicates an invalid reference. Any time the faulted signal transitions from 0 to 1 (that is, from nonfaulted to faulted), the validation timer is momentarily reset, which means that, once it is enabled, it must exhaust its full counting sequence before it expires. When faulted = 0 (that is, the reference is not faulted), the validation timer is allowed to perform its timing sequence. When faulted = 1 (that is, the reference is faulted), the validation timer is reset and halted. The faulted signal passes through an inverter, converting it to a nonfaulted signal, which appears at the input of the valid latch. This allows the valid latch to capture the state of the nonfaulted signal when the validation timer expires.
control bit in Register 0A0E. Writing a Logic 1 to any of these autoclearing bits triggers the valid latch, which is identically equivalent to a timeout of the validation timer.
REFERENCE PROFILES
The AD9548 has eight independent profile registers. A profile register contains 50 bytes that establish a particular set of device parameters. Each of the eight input references can be assigned to any one of the eight profiles (that is, more than one reference can be assigned to the same profile). The profiles allow the user to prescribe the specific device functionality that should take effect when one of the input references (assigned to the profile) becomes the active reference. Each profile register has the same format and stores the following device parameters: * * * * * * * * * * * * * * * Reference priority Reference period value (in femtoseconds) Inner tolerance value (1/tolerance) Outer tolerance value (1/tolerance) Validation timer value (milliseconds) Redetect timer value (milliseconds) Digital loop filter coefficients Reference prescaler setting (R-divider) Feedback divider settings (S, U, and V) DPLL phase lock detector threshold level DPLL phase lock detector fill rate DPLL phase lock detector drain rate DPLL frequency lock detector threshold level DPLL frequency lock detector fill rate DPLL frequency lock detector drain rate
*
*
*
The ref monitor bypass control bit enables bypassing of the ref fault signal generated by the reference monitor. When ref monitor bypass = 1, the state of the faulted signal is dictated by the ref monitor override control bit. This is useful when the user relies on an external reference monitor rather than the internal monitor resident in the device. The user programs the ref monitor override bit based on the status of the external monitor. On the other hand, when ref monitor bypass = 0, the ref monitor override control bit allows the user to manually test the operation of both the valid latch and the validation timer. In this case, the user relies on the signal generated by the internal reference monitor (ref fault) but uses the ref monitor override bit to emulate a faulted reference. That is, when ref monitor override = 1, then faulted = 1, but when ref monitor override = 0, then faulted = ref fault. In addition, the user has the ability to emulate a timeout of the validation timer via the appropriate force validation timeout
Reference-to-Profile Assignment Control
The user can manually assign a reference to a profile or let the device make the assignment automatically. The manual reference profile selection register (Address 0503 to Address 0506) is where the user programs whether a reference-to-profile assignment is manual or automatic. The manual reference profile selection register is a 4-byte register partitioned into eight half bytes (or nibbles). The eight nibbles form a one-toone correspondence with the eight reference inputs: one nibble for REF A, the next for REF AA, and so on. For a reference configured as a differential input, however, the device ignores the nibble associated with the two-letter input. For example, if
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AD9548
the B reference is differential, then only the REFB nibble matters (the device ignores the REFBB nibble). The MSB of each nibble is the manual profile bit, whereas the three LSBs of each nibble identify one of the eight profiles (0 to 7). A Logic 1 for the manual profile bit assigns the associated reference to the profile identified by the three LSBs of the nibble. A Logic 0 for the manual profile bit configures the associated reference for automatic reference-to-profile assignment (the three LSBs are ignored in this case). Note that references configured for automatic reference-to-profile assignment require activation (see the Reference-to-Profile Assignment State Machine section). The state machine activates immediately, unless the system clock is not stabilized, in which case, activation occurs upon expiration of the system clock stability timer. Note that initialization of the state machine is on a per-reference basis. That is, each reference input is associated with an independent initialization control bit. Once initialized for processing a reference, the state machine continuously monitors that reference until the occurrence of a device reset. This is true even when the user programs a reference for manual profile selection, in which case, the state machine associated with that particular reference operates with its activity masked. The masked background activity allows for seamless operation if the user subsequently reprograms the reference for automatic profile selection.
Reference-to-Profile Assignment State Machine
The functional flexibility of the AD9548 resides in the way that it assigns a particular input reference to one of the eight reference profiles. The reference-to-profile assignment state machine effectively builds a reference-to-profile table that maps the index of each input reference to a profile (see Table 22). Each entry in the profile column consists of a profile number (0 to 7) or a null value. A null value appears when a referenceto-profile assignment does not exist for a particular reference input (following a reset, for example). The information in Table 22 appears in the register map (Register 0D0C to Register 0D13) so that the user has access to the reference-to-profile assignments on a real-time basis. Register 0D0C contains the information for REF A, Register 0D0D contains the information for REF AA, and so on to Register 0D13 for REF DD. Bit 7 of each register is the null indicator for that particular reference. If Bit 7 = 0, then the profile assignment for that particular reference is null. If Bit 7 = 1, then that particular reference is assigned to the profile (0 to 7) identified by Bits[6:4]. Note that Bits[6:4] are meaningless unless Bit 7 = 1. Table 22. Reference-to-Profile Table
Reference Input A AA B BB C CC D DD Reference Index 0 1 2 3 4 5 6 7 Profile Profile number (or null value) Profile number (or null value) Profile number (or null value) Profile number (or null value) Profile number (or null value) Profile number (or null value) Profile number (or null value) Profile number (or null value)
Reference-to-Profile Assignment
When a reference is programmed for manual profile assignment (see Register 0503 to Register 0506), the reference-to-profile assignment state machine simply puts the programmed manual profile number into the profile column of the reference-toprofile table (see Table 22) in the row associated with the appropriate reference. However, when the user programs a reference for automatic profile assignment, the state machine must figure out which profile to assign to the reference. As long as a null entry appears in the reference-to-profile table for a particular input reference, the validation logic for that reference enters a period estimation mode. Note that a null entry is the default state following a reset, but it also occurs when a reference redetect timer expires. The period estimation mode enables the validation logic to make a blind estimate of the period of the input reference with a tolerance of 0.1%. The validation logic remains in the period estimation mode until it successfully estimates the reference period. Upon a successful reference period measurement by the validation logic, the state machine compares the measured period to the nominal reference period programmed into each of the eight profiles. The state machine assigns the reference to the profile with the closest match to the measured period. If more than one profile exactly matches the reference period, then the state machine chooses the profile with the lowest numeric index. For example, if the reference period in both Profile 3 and Profile 5 matches the measured period, then Profile 3 is given the assignment. To safeguard against making a poor reference-to-profile assignment, the state machine ensures that the measured reference period is within 6.25% of the nominal reference period that appears in the closest match profile. Otherwise, the state machine does not make a profile assignment and leaves the null entry in the reference-to-profile table. As long as there are input references programmed for automatic profile assignment, and for which the profile assignment is null, the state machine continues to cycle through those references searching for a profile match. Furthermore, unless an input
Following a reset, the reference-to-profile assignment state machine is inactive to avoid improperly assigning a reference to a profile before the system clock stabilizes. The reason is that the state machine relies on accurate information from the reference monitors, which, in turn, rely on a stable system clock. Because the reference-to-profile assignment state machine is inactive at power-up, the user must initiate it manually by writing to the reference profile detect register (Address 0A0D).
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reference is assigned to a profile, it is considered invalid and excluded as a candidate for a reference switchover.
Automatic Priority-Based Reference Switchover
The AD9548 has a two-tiered, automatic, priority-based algorithm that is in effect for both automatic and fallback reference switchover. The algorithm relies on the fact that each reference profile contains both a selection priority and a promoted priority. The selection and promoted priority values range from 0 (highest priority) to 7 (lowest priority). The selection priority determines the order in which references are chosen as the active reference. The promoted priority is a separate priority value given to a reference only after it becomes the active reference. An automatic reference switchover occurs on failure of the active reference or when a previously failed reference becomes valid and its selection priority is higher than the promoted priority of the currently active reference (assuming that the automatic or fallback reference switchover is in effect). When performing an automatic reference switchover, the AD9548 chooses a reference based on the priority settings within the profiles. That is, the device switches to the reference with the highest selection priority (lowest numeric priority value). It does so by using the reference-to-profile table (see Table 22) to determine the reference associated with the profile exhibiting the highest priority. If multiple references share the same profile, then the device chooses the reference having the lowest index value. For example, if the A, B, and CC references (Index 0, Index 2, and Index 5, respectively) share the same profile, then a switchover to Reference A occurs because Reference A has the lowest index value. Note, however, that only valid references are included in switchover of the selection process. The switchover control logic ignores any reference with a status indication of invalid. The promoted priority parameter allows the user to assign a higher priority to a reference after it becomes the active reference. For example, suppose four references have a selection priority of 3 and a promoted priority of 1, and the remaining references have a selection priority or 2 and a promoted priority of 2. Now, assume that one of the Priority 3 references becomes active because all of the Priority 2 references have failed. Sometime later, however, a Priority 2 reference becomes valid. The switchover logic normally attempts to automatically switch over to the Priority 2 reference because it has higher priority than the presently active Priority 3 reference. However, because the Priority 3 reference is active, its promoted priority of 1 is in effect. This is a higher priority than the newly validated reference's priority of 2, so the switchover does not occur. This mechanism enables the user to give references preferential treatment while they are selected as the active reference. An example of promoted vs. nonpromoted priority switching appears in state diagram form in Figure 35. Figure 36 shows a block diagram of the interrelationship between the reference inputs, monitors, validation logic, profile selection, and priority selection functionality.
REFERENCE SWITCHOVER
An attractive feature of the AD9548 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover. The main reference switchover control resides in the loop mode register (Address 0A01). The user selection mode bits (Register 0A01, Bits[4:3]) allow the user to select one of the reference switchover state machine's four operating modes, as follows: * * * * Automatic mode (Address A01, Bits[4:3] = 00) Fallback mode (Address 0A01, Bits[4:3] = 01) Holdover mode (Address 0A01, Bits[4:3] = 10) Manual mode (Address 0A01, Bits[4:3] = 11)
In automatic mode, a fully automatic priority-based algorithm selects which reference is the active reference. When programmed for automatic mode, the device ignores the user selection reference bits (Register 0A01, Bits[2:0]). However, when programmed for any of the other three modes, the device makes use of the user reference bits. These bits specify a particular input reference (000 = REF A, 001 = REF AA ..., 111 = REF DD). In fallback mode, the user reference is the active reference whenever it is valid. Otherwise, the device switches to a new reference using the automatic, priority-based algorithm. In holdover mode, the user reference is the active reference whenever it is valid. Otherwise, the device switches to holdover mode. In manual mode, the user reference is the active reference whether it is valid or not. Note that, when using this mode, the user must program the reference-to-profile assignment (see register 0503 to Register 0506) as manual for the particular reference declared as the user reference. The reason is that if the user reference fails and its redetect timer expires, then its profile assignment (shown in Table 22) becomes null. This means that the active reference (user reference) does not have an assigned profile, which places the AD9548 into an undefined state. The user also has the option to force the device directly into holdover or free-run operation via the user holdover and user free-run bits (Register 0A01, Bit 6 and Bit 5, respectively]). In free-run mode, the free running frequency tuning word register (Address 0300 to Address 0305) defines the DDS output frequency. In holdover mode, the DDS output frequency depends on the holdover control settings (see the Holdover section).
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AD9548
INITIAL STATE A ACTIVE
ALL VALID
PRIORITY TABLE
INPUT A B C D PRIORITY 0 1 2 3 PROMOTED 0 0 1 2
A VALID
A FAULTED
B ACTIVE
A VALID
B VALID
B FAULTED
B VALID
Figure 35. Example of Priority Promotion
PROFILE SELECTION A/AA
VALIDATION LOGIC
PRIORITY SELECTION
LOOP CONTROLLER
.........
B/BB C/CC D/DD
MONITORS
......
...
08022-011
COMMON WITHOUT PROMOTION WITH PROMOTION
C ACTIVE
/R
TDC
08022-012
Figure 36. Reference Clock Block Diagram
Phase Build-Out Reference Switching
Phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. That is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs. The AD9548 handles phase build-out switching based on whether the new reference is a phase master. A phase master is any reference with a selection priority value that is less than the phase master threshold priority value (that is, higher priority). The phase master threshold priority value resides in the phase build-out switching register (Address 0507), whereas the selection priority resides in the profile registers (Address 0600 to Address 07FF). By default, the phase master threshold priority is 0; therefore, no references can be phase masters until the user changes the phase master threshold priority. Whenever the AD9548 switches from one reference to another, it compares the selection priority value stored in the profile assigned to the new reference with the phase master threshold priority. The AD9548 performs a phase build-out switchover only if the new reference is not a phase master.
The all-digital nature of the DPLL core (see the Digital PLL (DPLL) Core section) gives the user numerical control of the rate at which phase changes occur at the DPLL output. When enabled, a phase slew controller monitors the phase difference between the feedback and reference inputs to the DPLL. The phase slew controller has the ability to place a user-specified limit on the rate of change of phase, thus providing a mechanism for hitless reference switching. The user sets a limit on the rate of change of phase by storing the appropriate value in the 16-bit phase slew rate limit register (Address 0316 to Address 0317). The 16-bit word (representing ns/sec) puts an upper bound on the rate of change of the phase at the output of the DPLL during a reference switchover. A phase slew rate value of 0 (default) disables the phase slew controller. The accuracy of the phase slew controller depends on both the phase slew limit value and the system clock frequency. Generally, an increase in the phase slew rate limit value or a decrease in the system clock frequency tends to reduce the error. As such, the accuracy is best for the largest phase slew limit value and the lowest system clock frequency. For example, assuming the use of a 1 GHz system clock, a phase slew limit value of 315 ns/sec (or more) ensures an error of less than 10%, whereas a phase slew rate limit value above ~3100 ns/sec ensures an error of less than 1%. On the other hand, assuming the use of a 500 MHz system clock, the same phase slew rate limit values ensure an error of less than 5% or 0.5%, respectively.
Hitless Reference Switching (Phase Slew Control)
Hitless reference switching is the term given to a reference switchover that limits the rate of change of the phase of the output clock while the PLL is in the process of acquiring phase lock. This prevents the output frequency offset from becoming excessive.
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AD9548
DIGITAL PLL (DPLL) CORE
DPLL Overview
A diagram of the digital PLL core of the AD9584 appears in Figure 37. The phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that comprise this second generation DPLL are all digital implementations.
LOCK DETECT PHASE SLEW LIMIT REF A fR REF DD DPPL CORE CLOSED-LOOP PHASE OFFSET
The DPLL includes a feedback divider that causes the DDS to operate at an integer-plus-fractional multiple (S + 1 + U/V) of fTDC. S is the 30-bit value stored in the profile register and has a range of 7 S 1,073,741,823. U and V are the 10-bit numerator and denominator values of the optional fractional divide component and are also stored in the profile register. Together they establish the nominal DDS frequency (fDDS), given by
f DDS =
fR U S +1+ R +1 V
R+1
fTDC
TDC AND PFD DIGITAL LOOP FILTER DDS/ DAC
fDDS
2
DACOUT
S + 1 + U/V
Figure 37. Digital PLL Core
The start of the DPLL signal chain is the reference signal, fR, which is the frequency of the reference input. A reference prescaler reduces the frequency of this signal by an integer factor, R + 1, where R is the 30-bit value stored in the appropriate profile register and 0 R 1,073,741,823. Therefore, the frequency at the output of the R-divider (or the input to TDC) is
Normally, fractional-N designs exhibit distinctive phase noise and spurious artifacts resulting from the modulation of the integer divider based on the fractional value. Such is not the case for the AD9548 because it uses a purely digital means to determine phase errors. Because the phase errors incurred by modulating the feedback divider are deterministic, it is possible to compensate for them digitally. The result is a fractional-N PLL with no discernable modulation artifacts.
08022-013
TDC/PFD
The TDC is a highly integrated functional block that incorporates both analog and digital circuitry. There are two pins associated with the TDC that the user must connect to external components. Figure 38 shows the recommended component values and their connections. For best performance, place components as close as possible to the device pins. Components with low effective series resistance (ESR) and low parasitic inductance yield the best results.
AD9548
57 58
f TDC =
fR R +1
A time-to-digital converter (TDC) samples the output of the R-divider. The TDC/PFD produces a time series of digital words and delivers them to the digital loop filter. The digital loop filter offers the following advantages: * * * * Determination of the filter response by numeric coefficients rather than by discrete component values The absence of analog components (R/L/C), which eliminates tolerance variations due to aging The absence of thermal noise associated with analog components The absence of control node leakage current associated with analog components (a source of reference feedthrough spurs in the output spectrum of a traditional analog PLL)
TDC_VRB 0.1F
TDC_VRT
10F
Figure 38. TDC Pin Connections
The digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a DDS, with the DDS replacing the function of the VCO in an analog PLL. The digital words from the loop filter tend to steer the DDS frequency toward frequency and phase lock with the input signal (fTDC). The DDS provides an analog output signal via an integrated DAC, effectively mimicking the operation of an analog VCO.
The phase-frequency detector (PFD) is an all-digital block. It compares the digital output from the TDC (which relates to the active reference edge) with the digital word from the feedback block (which relates to the rollover edge of the DDS accumulator after division by the feedback divider). It uses a digital code pump and digital integrator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the DDS frequency toward phase lock.
Closed-Loop Phase Offset
The all-digital nature of the TDC/PFD provides for numerical control of the phase offset between the reference and feedback edges. This allows the user to adjust the relative timing of the distribution output edges relative to the reference input edges by programming the 40-bit fixed phase lock offset register
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08022-014
0.1F
0.1F
AD9548
(Address 030F to Address 0313). The 40-bit word is a signed (twos complement) number that represents units of picoseconds. In addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion. To do so, program the desired step size in the 16-bit incremental phase lock offset step size register (Address 0314 to Address 0315). This is an unsigned number that represents units of picoseconds. The programmed step size is added to the current closed-loop phase offset each time the user writes a Logic 1 to the increment phase offset bit (Register 0A0C, Bit 0). Conversely, the programmed step size is subtracted from the current closed-loop phase offset each time the user writes a Logic 1 to the decrement phase offset bit (Register 0A0C, Bit 1). The serial I/O port control logic clears both of these bits automatically. The user can remove the incrementally accumulated phase by writing a Logic 1 to the reset incremental phase offset bit (Register 0A0C, Bit 2), which is also cleared automatically. Alternatively, rather than using the serial I/O port, the multifunction pins can be set up to perform the increment, decrement, and clear functions. Note that the incremental phase offset is completely independent of the offset programmed into the fixed phase lock offset register. However, if the phase slew limiter is active (see the Hitless Reference Switching (Phase Slew Control) section), then any instantaneous change in closed-loop phase offset (fixed or incremental) will be subject to possible slew limitation by the action of the phase slew limiter. also has an exponential component representing a power of 2 with a negative exponent. That is, the user enters a positive number (x) that the hardware interprets as a negative exponent of two (2-x). Thus, the , , and coefficients always represent values less than unity. The coefficient, however, has two additional exponential components, but the hardware interprets these as a positive exponent of 2 (that is, 2x). This allows the coefficient to be a value greater than unity. The positive exponent appears as two separate terms in order to provide sufficient dynamic range.
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers. The phase lock detector behaves in a manner analogous to water in a tub (see Figure 41). The total capacity of the tub is 4096 units with -2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. The tub also has a safeguard to prevent overflow. Furthermore, the tub has a low water mark at -1024 and a high water mark at +1024. To change the water level, the user adds water with a fill bucket or removes water with a drain bucket. The user specifies the size of the fill and drain buckets via the 8-bit fill rate and drain rate values in the profile registers. The water level in the tub is what the lock detector uses to determine the lock and unlock conditions. Whenever the water level is below the low water mark (-1024), the detector indicates an unlock condition. Conversely, whenever the water level is above the high water mark (+1024), the detector indicates a lock condition. While the water level is between the marks, the detector simply holds its last condition. This concept appears graphically in Figure 41, with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states. During any given PFD phase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision of whether to add or remove water depends on the threshold level specified by the user. The phase lock threshold value is a 16-bit number stored in the profile registers and is expressed in picoseconds. Thus, the phase lock threshold extends from 0 ns to 65.535 ns and represents the magnitude of the phase error at the output of the PFD. The phase lock detector compares each phase error sample at the output of the PFD to the programmed phase threshold value. If the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, then the detector control logic dumps one fill bucket into the tub. Otherwise, it removes one drain bucket from the tub. Notice that it is not the polarity of the phase error sample, but its magnitude relative to the phase threshold value, that determines whether to fill or drain. If more filling is taking place than
Programmable Digital Loop Filter
The AD9548 loop filter is a third order digital IIR filter that is analogous to the third order analog loop shown in Figure 39.
R3
08022-015
C1
R2 C2
C3
Figure 39. Third Order Analog Loop Filter
The filter requires four coefficients as shown in Figure 40. The AD9548 evaluation board software automatically generates the required loop filter coefficient values based on the user's design criteria. The Calculating Digital Filter Coefficients section contains the design equations for calculating the loop filter coefficients manually.
FRACTIONAL (16-BIT) 1/2x (6-BIT) 2x (3-BIT) 2x (4-BIT) FRACTIONAL (17-BIT) 1/2x (6-BIT) FRACTIONAL (17-BIT) 1/2x (6-BIT) FRACTIONAL (15-BIT) 1/2x (5-BIT)
51 IN
Figure 40. Third Order Digital IIR Loop Filter
Each coefficient has a fractional component representing a value from 0 up to, but not including, unity. Each coefficient
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LOOP FILTER (THIRD ORDER IIR)
48 OUT
AD9548
draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. If more draining is taking place than filling, then the water level in the tub eventually falls below the low water mark (-1024), which causes the phase lock detector to indicate unlock. The ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the phase lock detector to the statistics of the timing jitter associated with the input reference signal.
PREVIOUS STATE 2048 1024 0 -1024 -2048
FILL RATE DRAIN RATE
08022-017
DIRECT DIGITAL SYNTHESIZER
DDS Overview
One of the primary building blocks of the digital PLL is a direct digital synthesizer (DDS). The DDS behaves like a sinusoidal signal generator. The frequency of the sinusoid generated by the DDS is determined by a frequency tuning word (FTW), which is a digital (that is, numeric) value. Unlike an analog sinusoidal generator, a DDS uses digital building blocks and operates as a sampled system. Thus, it requires a sampling clock (fS) that serves as the fundamental timing source of the DDS. The accumulator behaves as a modulo-248 counter with a programmable step size (FTW). A block diagram of the DDS appears in Figure 42. The input to the DDS is the 48-bit FTW. The FTW serves as a step size value. On each cycle of fS, the accumulator adds the value of the FTW to the running total at its output. For example, given FTW = 5, the accumulator counts by fives, incrementing on each fS cycle. Over time, the accumulator reaches the upper end of its capacity (248 in this case), at which point, it rolls over but retains the excess. The average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. The average rollover rate of the accumulator establishes the output frequency (fDDS) of the DDS and is given by
LOCKED
UNLOCKED
LOCK LEVEL
UNLOCK LEVEL
Figure 41. Lock Detector Diagram
Note that whenever the AD9548 enters the free-run or holdover mode, the DPLL phase lock detector indicates unlocked. In addition, whenever the AD9548 performs a reference switchover, the state of the lock detector prior to the switch is preserved during the transition period.
DPLL Frequency Lock Detector
The operation of the frequency lock detector is identical to that of the phase lock detector. The only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the DPLL instead of the phase error at the output of the PFD. The frequency lock detector uses a 24-bit frequency threshold register specified in units of picoseconds. Thus, the frequency threshold value extends from 0 s to 16.777215 s. It represents the magnitude of the difference in period between the reference and feedback signals at the input to the DPLL. For example, if the reference signal is 1.25 MHz and the feedback signal is 1.38 MHz, then the period difference is approximately 75.36 ns (|1/1,250,000 - 1/1,380,000| 75.36 ns).
48-BIT ACCUMULATOR 48 48 48 D Q PHASE OFFSET 16 19 19
FTW f DDS = 48 f S 2 Solving this equation for FTW yields
f FTW = round 2 48 DDS fS

For example, given that fS = 1 GHz and fDDS = 155.52 MHz, then FTW = 437,749,988,378,041 (0x27D028A1DFB9). Note that the minimum DAC output frequency is 62.5 MHz; therefore, normal operation requires an FTW that yields an output frequency in excess of this lower bound.
FREQUENCY TUNING WORD (FTW)
ANGLE TO AMPLITUDE CONVERSION
14
DAC (14-BIT)
DAC+ DAC-
fS
Figure 42. DDS Block Diagram
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AD9548
DDS Phase Offset
The relative phase of the sinusoid generated by the DDS is numerically controlled by adding a phase offset word to the output of the DDS accumulator. This is accomplished via the open loop phase offset register (Address 030D to Address 030E), which is a programmable 16-bit value (phase). The resulting phase offset, (in radians), is given by
TUNING WORD HISTORY FREE-RUN TUNING WORD TUNING WORD UPDATE FROM DIGITAL LOOP FILTER TUNING WORD ROUTING CONTROL TUNING WORD CLAMP LOWER TUNING WORD UPPER TUNING WORD TO DDS TUNING WORD HISTORY PROCESSOR
phase = 2 16 2
Phase offset and relative time offset are directly related. The time offset is (phase/216)/fDDS (in seconds), where fDDS is the output frequency of the DDS (in hertz).
Figure 44. Tuning Word Processing
DAC Output
The output of the digital core of the DDS is a time series of numbers representing a sinusoidal waveform. The DAC translates the numeric values to an analog signal. The DAC output signal appears at two pins that constitute a balanced current source architecture (see Figure 43).
AVDD3
21 22
When the DPLL is in free-run mode, the DDS tuning word is the value stored in the free running frequency tuning word register (Address 0300 to Address 0305). When the DPLL is operating normally (closed loop), the DDS tuning word comes from the output of the digital loop filter, which changes dynamically in order to maintain phase lock with the input reference signal (assuming that the device has not performed an automatic switch to holdover mode). When the DPLL is in holdover mode, the DDS tuning word depends on a historical record of past tuning words during the time that the DPLL operated in closed-loop mode. However, regardless of the operating mode, the DDS output frequency is ultimately subject to the boundary conditions imposed by the frequency clamp logic, as explained in the Frequency Clamp section.
10 ISCALE
CURRENT MIRROR IFS CURRENT SWITCH ARRAY
Frequency Clamp
The user controls the frequency clamp boundaries via the pullin range limits registers (Address 0307 to Address 030C). These registers allow the user to fix the DDS output frequency between an upper and lower bound with a granularity of 24 bits. Note that these upper and lower bounds apply regardless of the frequency tuning word that appears at the input to the DDS. The register value relates to the absolute upper or lower frequency bound (fCLAMP) as fCLAMP = fS x (N/224) Where N is the value stored in the upper- or lower-limit register,and fS is the system sample rate. Even though the frequency clamp limits put a bound on the DDS output frequency, the DPLL is still free to steer the DDS frequency within the clamp limits. The default register values set the clamp range from 0 Hz (dc) to fS, effectively eliminating the frequency clamp functionality until the user alters the register values.
IFS (
CODE
214 - 1
)
IFS (1-
CODE
214 - 1
)
DACOUTP 18
SWITCH CONTROL
19 DACOUTN
50
14 CODE
50
GND
GND
Figure 43. DAC Output Pins
The value of IFS is programmable via the 10-bit DAC full-scale current word in the DAC current register (Address 0213 to Address 0214). The value of the 10-bit word (ISCALE) sets IFS according to the following formula:
3 I FS = 120 A x 72 + 16 I SCALE
(
()
)
08022-019
TUNING WORD PROCESSING
The frequency tuning words that dictate the output frequency of the DDS come from one of three sources (see Figure 44). * * * The free running frequency tuning word register The output of the digital loop filter The output of the tuning word history processor
Frequency Tuning Word History
The AD9548 has the ability to track the history of the tuning word samples generated by the DPLL digital loop filter output. It does so by periodically computing the average tuning word value over a user-specified interval. The user programs the interval via the 24-bit history accumulation timer register (Address 0318 to Address 031A). This 24-bit value represents a time interval (TAVG) in milliseconds that extends from 1 ms to a maximum of 4:39:37.215 (hr:min:sec).
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Note that history accumulation timer = 0 should not be programmed because it may cause improper device operation. The control logic performs a calculation of the average tuning word during the TAVG interval and stores the result in the holdover history register (Address 0D14 to Address 0D19). Computation of the average for each TAVG interval is independent of the previous interval (that is, the average is a memoryless average as opposed to a true moving average). In addition, at the end of each TAVG interval, the device generates an internal strobe pulse. The strobe pulse sets the history updated bit in the IRQ monitor register (assuming the bit is enabled via the IRQ mask register). Furthermore, the strobe pulse is available as an output signal via the multifunction pins (see the Multifunction Pins (M0 to M7) section). History accumulation begins whenever the device switches to a new reference. By default, the device clears any previous history when it switches to a new reference. Furthermore, the user can clear the tuning word history under software control via Register 0A03, Bit 2, or under hardware control via the multifunction pins (see the Multifunction Pins (M0 to M7) section). However, the user has the option of programming the device to retain (rather than clear) the old history by setting the persistent history bit (Register 031B, Bit 3). Whenever the tuning word history is nonexistent (that is, after a power-up, reset, or switchover to a new reference with the persistent history bit cleared), the device waits for the history accumulation timer (TAVG) to expire before storing the first history value in the holdover history register. In cases where TAVG is quite large (41/2 hours, for example), a problem arises in that the first averaged result does not become available until the full TAVG interval passes. Thus, it is possible that as much as 41/2 hours can elapse before the first averaged result is available. If the device has to switch to holdover mode during this time, a tuning word history is not available. To alleviate this problem, the user has access to the incremental average bits in the history mode register (Register 031B, Bits[2:0]). If the history has been cleared, then this 3-bit value, K (0 K 7), specifies the number of intermediate averages to take during the first, and only the first, TAVG interval. When K = 0, no intermediate averages are calculated; therefore, the first average occurs after interval TAVG (the default operating mode). However, if K = 4, for example, four intermediate averages are taken during the first TAVG interval. These average computations occur at TAVG/16, TAVG/8, TAVG/4, TAVG/2, and TAVG (notice that the denominator exhibits a sequence of powers of 2 beginning with TAVG/2K). The calculation of intermediate averages occurs only during the first TAVG interval. All subsequent average computations occur at evenly spaced intervals of TAVG.
LOOP CONTROL STATE MACHINE
The loop control state machine is responsible for monitoring, initiating, and sequencing changes to the DPLL loop. Generally, it automatically controls the transition between input references and the entry and exit of holdover mode. In controlling loop state changes, the state machine also arbitrates the application of new loop filter coefficients, divider settings, and phase detector offsets based on the profile settings. The user can manually force the device into holdover or free-run mode via the loop mode register (Address 0A01), as well as force the selection of a specific input reference.
Switchover
Switchover occurs when the loop controller switches directly from one input reference to another. Functionally, the AD9548 handles a reference switchover by briefly entering holdover mode and then immediately recovering. During the switchover event, however, the AD9548 preserves the status of the lock detectors to avoid phantom unlock indications.
Holdover
The holdover state of the DPLL is an open-loop operating mode. That is, the device no longer operates as a closed-loop system. Instead, the output frequency remains constant and is dependent on the device programming and availability of tuning word history. If a tuning word history exists (see the Frequency Tuning Word History section), then the holdover frequency is the average frequency just prior to entering the holdover state. If there is no tuning word history, then the holdover frequency depends on the state of the single sample fallback bit in the history mode register (Register 031B, Bit 4). If the single sample fallback bit is Logic 0, then the holdover frequency is the frequency defined in the free running frequency tuning word register (Address 0300 to Address 0305). If the single sample fallback bit is Logic 1, then the holdover frequency is the last instantaneous frequency output by the DDS just prior to the device entering holdover mode (note that this is not the average frequency prior to holdover). The initial holdover frequency accuracy depends on the loop bandwidth of the DPLL and the time elapsed to compute a tuning word history. The longer the historical average, the more accurate the initial holdover frequency (assuming a drift-free system clock). Furthermore, the stability of the system clock establishes the stability and long-term accuracy of the holdover output frequency. Another consideration is the 48-bit frequency tuning resolution of the DDS and its relationship to fractional frequency error, fO/fO, as follows:
f f O = 49 S fO 2 fO
where, fS is the sample rate of the output DAC, and fO is the DDS output frequency.
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The worst-case scenario is maximum fS (1 GHz) and minimum fO (62.5 MHz), which yields fO/fO = 2.8 x 10-14, less than one part in 10 trillion.
System Clock Period
Many of the user-programmable parameters of the AD9548 have absolute time units. To make this possible, the AD9548 requires a priori knowledge of the period of the system clock. To accommodate this requirement, the user programs the 21-bit nominal system clock period in the nominal SYSCLK period register (Address 0106 to Address 0108). The contents of this register reflect the actual period of the system clock in femtoseconds. The user must properly program this register to ensure proper operation of the device because many of its subsystems rely on this value.
Recovery from Holdover
When in holdover and a valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference. Note that, if the user holdover bit (Register 0A01, Bit 6) is set, the device does not automatically exit holdover when a valid reference is available. However, automatic recovery can occur after clearing the user holdover bit.
System Clock Details
A block diagram of the system clock appears in Figure 45. The signal at the SYSCLKx input pins becomes the internally buffered DAC sampling clock (fS) via one of three paths. * * * High frequency direct (HF) Low frequency synthesized (LF) Crystal resonator synthesized (XTAL)
SYSTEM CLOCK INPUTS
Functional Description
The system clock circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The user has the option of directly driving the SYSCLKx inputs with a high frequency clock source at the desired system clock rate. Alternatively, the SYSCLKx input can be configured to operate in conjunction with the internal SYSCLK PLL. The SYSCLK PLL can synthesize the system clock by means of a crystal resonator connected across the SYSCLKx input pins or by means of direct application of a low frequency clock source. The SYSCLKx inputs are internally biased to a dc level of ~1 V. Take care to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. Generally, the recommendation is that the SYSCLKx inputs be ac-coupled to the signal source (except when using a crystal resonator).
Note that both the LF and XTAL paths require the use of the SYSCLK PLL (see the SYSCLK PLL Multiplier section). The main purpose of the HF path is to allow the direct use of a high frequency (500 MHz to 1 GHz) external clock source for clocking the AD9548. This path is optimized for high frequency and low noise floor. Note that the HF input also provides a path to SYSCLK PLL (see the SYSCLK PLL Multiplier section), which includes an input divider (M) programmable for divideby -1, -2, -4, or -8. The purpose of the divider is to limit the frequency at the input to the PLL to less than 150 MHz (the maximum PFD rate).
SYSCLK_VREG
48
SYSCLK_LF
49
LF
2x
LOCK DETECT
VCO CALIBRATION
SYSCLKN 52
XTAL /M
PFD AND CHARGE PUMP
LOOP FILTER
SYSCLKP 53
/N HF
SYSTEM CLOCK
Figure 45. System Clock Block Diagram
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AD9548
The LF path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 MHz up to 100 MHz. However, when using a sinusoidal input signal, it is best to use a frequency in excess of 20 MHz. Otherwise, the resulting low slew rate can lead to substandard noise performance. Note that the LF path includes an optional 2x frequency multiplier to double the rate at the input to the SYSCLK PLL and potentially reduce the PLL in-band noise. However, to avoid exceeding the maximum PFD rate of 150 MHz, using the 2x frequency multiplier is valid only for input frequencies below 125 MHz. The XTAL path enables the connection of a crystal resonator (typically 10 MHz to 50 MHz) across the SYSCLKx input pins. An internal amplifier provides the negative resistance required to induce oscillation. The internal amplifier expects a 3.2 mm x 2.5 mm AT cut, fundamental mode crystal with a maximum motional resistance of 100 . The following crystals, listed in alphabetical order, may meet these criteria. Note that, whereas these crystals may meet the preceding criteria according to their data sheets, Analog Devices, Inc., does not guarantee their operation with the AD9548 nor does Analog Devices endorse one crystal manufacturer/supplier over another. * * * * * * AVX/Kyocera CX3225SB ECS ECX-32 Epson/Toyocom TSX-3225 Fox FX3225BS NDK NX3225SA Siward SX-3225 Note that 0 must be written to the system clock stability timer (Register 0106 to Register 0108) whenever the lock detector is disabled (Register 0100, Bit 2 = 1). The SYSCLK PLL phase detector operates at the PFD rate, which is fVCO/N. Each PFD sample indicates whether the reference and feedback signals are phase aligned (within a certain threshold range). While the PLL is in the process of acquiring a lock condition, the PFD samples typically consist of an arbitrary sequence of in-phase and out-of-phase indications. As the PLL approaches complete phase lock, the number of consecutive in-phase PFD samples grows larger. Thus, one way of indicating a locked condition is to count the number of consecutive in-phase PFD samples and if it exceeds a certain value, then declare the PLL locked. This is exactly the role of the lock detect divider bits. When the lock detector is enabled (Register 0100, Bit 2 = 0), the lock detect divider bits determine the number of consecutive in-phase decisions required (128, 256, 512, or 1024) before the lock detector declares a locked condition. The default setting is 128.
Charge Pump
The charge pump operates in either automatic or manual mode based on the charge pump mode bit (Register 0100, Bit 6). When Register 0100, Bit 6 = 0, the AD9548 automatically selects the appropriate charge pump current based on the N-divider value. Note that the user cannot control the charge pump current bits (Register 0100, Bits[5:3]) in automatic mode. When Register 0100, Bit 6 = 1, the user determines the charge pump current via the charge pump current bits (Register 0100, Bits[5:3]). The charge pump current varies from 125 A to 1 mA in 125 A steps. The default setting is 500 A.
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on an integrated LC tank and VCO. It provides a means to convert a low frequency clock input to the desired system clock frequency, fS (900 MHz to 1 GHz). The SYSCLK PLL multiplier accepts input signals between 3.5 MHz and 500 MHz, but frequencies in excess of 150 MHz require the M-divider to ensure compliance with the maximum PFD rate (150 MHz). The PLL contains a feedback divider (N) that is programmable for divide values between 6 and 255. The nominal VCO gain is 70 MHz/V.
SYSCLK PLL Loop Filter
The AD9548 has an internal second order loop filter that establishes the loop dynamics for input signals between 12.5 MHz and 100 MHz. By default, the device uses the internal loop filter. However, an external loop filter option is available by setting the external loop filter enable bit (Register 0100, Bit 7). This bypasses the internal loop filter and allows the device to use an externally connected second order loop filter, as shown in Figure 46.
AD9548
SYSCLK_VREG
48
R1
08022-021
Lock Detector
The SYSCLK PLL has a built-in lock detector. Register 0100, Bit 2 determines whether the lock detector is active. When active (default), the user controls the sensitivity of the lock detector via the lock detect divider bits (Register 0100, Bits[1:0]).
SYSCLK_LF
49
C1 C2
Figure 46. External Loop Filter Schematic
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To determine the external loop filter components, the user decides on the desired open loop bandwidth (fOL) and phase margin (). These parameters allow calculation of the loop filter components, as follows:
R1 = 1 NfOL 1 + I CP KVCO sin ( )
of the timer indicates that the SYSCLK PLL is stable, which is reflected in the system clock register (Register 0D01, Bit 4). Note that the monitors/detectors associated with the input references (REFA/AA - REFD/DD) are internally disabled until the SYSCLK PLL indicates that it is stable.
CLOCK DISTRIBUTION
The clock distribution block of the AD9548 provides an integrated solution for generating multiple clock outputs based on frequency dividing the DPLL output. The distribution output consists of four channels (OUT0 to OUT3). Each of the four output channels has a dedicated divider and output driver, as appears in Figure 47.
CLKINP CLKINN
C1 = C2 =
I CP KVCO tan() 2 2 N (fOL ) I CP KVCO 1 - sin ( ) 2 N (2f OL ) cos( )
where KVCO = 7 x 107 V/ns (typical), ICP is the programmed charge pump current (amperes), N is the programmed feedback divider value, fOL is the desired open-loop bandwidth (in hertz), and is the desired phase margin (in radians). For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz, and = 50, then the loop filter calculations yield R1 = 3.31 k, C1 = 330 pF, and C2 = 50.4 pF.
SYNC CONTROL
ENABLE RESET
SYNC SOURCE
System Clock Stability Timer
The system clock stability timer (Register 0106 to Register 0108) is a 20-bit value programmed in milliseconds. If the programmed timer value is 0, then the timer immediately indicates that it has timed out. If the programmed timer value is a nonzero value and the SYSCLK PLL is enabled, then the timer starts timing when the SYSCLK PLL lock detector indicates lock and times out after the prescribed period. However, when the user disables the SYSCLK PLL, then the timer ignores the SYSCLK PLL lock detector and starts timing as soon as the SYSCLK PLL is disabled. The user can monitor the status of the stability timer via Register 0D01, Bit 4, via the multifunction pins or via the IRQ pin. Note that the system clock stability timer must be programmed before the SYSCLK PLL is either activated or disabled.
ENABLE n/MODEn 4 4 OUT_RSET
4
Q0
OUT0P OUT0N OUT0 OUT1 OUT2 OUT3 OUT1P OUT1N OUT2P OUT2N
08022-022
OUT3P OUT3N
Figure 47. Clock Distribution
Clock Input (CLKINx)
The clock input handles input signals from a variety of logic families (assuming proper terminations and sufficient voltage swing). It also handles sine wave input signals such as those delivered by the DAC reconstruction filter. Its default operating frequency range is 62.5 MHz to 500 MHz.
SYSCLK PLL Calibration
When using the SYSCLK PLL, it is necessary to calibrate the LC VCO to ensure that the PLL can remain locked to the system clock input signal. Assuming the presence of either an external SYSCLK input signal or a crystal resonator, the calibration process executes after the user sets and then clears the calibrate system clock bit in the cal/sync register (Register 0A02, Bit 0). During the calibration process, the device calibrates the VCO amplitude and frequency. The status of the system clock calibration process is user accessible via the system clock register (Register 0D01, Bit 1). It is also available via the IRQ monitor register (Register 0D02, Bit 1) provided the status bit is enabled via the IRQ mask register. When the calibration sequence is complete, the SYSCLK PLL eventually attains a lock condition, at which point the system clock stability timer begins its countdown sequence. Expiration
Super-Nyquist Operation
Typically, the maximum usable frequency at the DAC output is about 45% of the system clock frequency. However, because it is a sampled DAC, its output spectrum contains Nyquist images. Of particular interest are the images appearing in the first Nyquist zone (50% to 100% of the system clock frequency). SuperNyquist operation takes advantage of these higher frequencies, but this implies that the CLKINx input operates in excess of 500 MHz, which is outside of its default operating limits. The CLKINx receiver actually consists of two separate receivers: the default receiver and an optional high frequency receiver,
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which handles input signals up to 800 MHz. To select the high frequency receiver, write a Logic 1 to Register 0400, Bit 4. Super-Nyquist operation requires a band-pass filter at the DAC output instead of the usual low-pass reconstruction filter. Super-Nyquist operation is viable as long as the image frequency does not exceed the 800 MHz input range of the receiver. Furthermore, to provide acceptable jitter performance, which is a consideration for image signals with low amplitude, the signal at the CLKINx input must meet the minimum slew rate requirements. * In LVDS/LVPECL mode, place the output in tristate mode (this works in CMOS mode as well).
Output Enable
Each of the output channels offers independent control of enable/ disable functionality via the distribution enable register (Address 0401). The distribution outputs use synchronization logic to control enable/disable activity to avoid the production of runt pulses and ensure that outputs with the same divide ratios become active/inactive in unison.
Clock Dividers
The output clock distribution dividers are referred to as Q0 to Q3, corresponding to the OUT0 to OUT3 output channels, respectively. Each divider is programmable with 30 bits of division depth. The actual divider ratio is one more than the programmed register value; therefore, a register value of 3, for example, results in a divide ratio of 4. Thus, each divider offers a range of divide ratios from 1 to 230 (1 to 1,073,741,824). With an even divide ratio, the output signal always exhibits a 50% duty cycle. When the clock divider is bypassed (a divide ratio of 1), the output duty cycle is the same as the input duty cycle. Odd output divide ratios (excluding 1) exhibit automatic duty cycle correction given by
Output Duty Cycle = N + 2 X -1 2N
Output Mode
The user has independent control of the operating mode of each of the four output channels via the distribution channel modes register (Address 0404 to Address 0407). The operating mode control includes * * * Logic family and pin functionality Output drive strength Output polarity
The three least significant bits of each of the four distribution channel mode registers comprise the mode bits. The mode value selects the desired logic family and pin functionality of an output channel, as given in Table 23.
Table 23. Output Channel Logic Family and Pin Functionality
Mode Bits [2:0] 000 001 010 011 100 101 110 111 Logic Family and Pin Functionality CMOS (both pins) CMOS (positive pin); tristate (negative pin) Tristate (positive pin); CMOS (negative pin) Tristate (both pins) LVDS LVPECL Unused Unused
where N (which must be an odd number) is the divide ratio and X is the normalized fraction of the high portion of the input period (that is, 0 < X < 1). For example, if N = 5 and the input duty cycle is 20% (X = 0.2), then the output duty cycle is 44%. Note that, when the user programs an output as noninverting, then the device adjusts the falling edge timing to accomplish the duty cycle correction. Conversely, the device adjusts the rising edge timing for an inverted output.
Output Power-Down
Each of the output channels offers independent control of power-down functionality via the distribution settings register (Address 0400). Each output channel has a dedicated powerdown bit for powering down the output driver. However, if all four outputs are powered down, the entire distribution output enters a deep sleep mode. Even though each channel has a channel power-down control signal, it may sometimes be desirable to power down an output driver while maintaining the divider's synchronization with the other channel dividers. This is accomplished by either of the following methods: * In CMOS mode, use the divider output enable control bit to stall an output. This provides power savings while maintaining dc drive at the output.
Regardless of the selected logic family, each is capable of dc operation. However, the upper frequency is limited by the load conditions, drive strength, and impedance matching inherent in each logic family. Practical limitations set the maximum CMOS frequency to approximately 250 MHz, whereas LVPECL and LVDS are capable of 725 MHz. In addition to the three mode bits, each of the four distribution channel mode registers includes the following control bits: * * * Polarity invert CMOS phase invert Drive strength
The polarity invert bit enables the user to choose between normal polarity and inverted polarity. Normal polarity is the default state. Inverted polarity reverses the representation of Logic 0 and Logic 1 regardless of the logic family. The CMOS phase invert bit applies only when the mode bits select the CMOS logic family. In CMOS mode, both output pins
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of the channel have a dedicated CMOS driver. By default, both drivers deliver identical signals. However, setting the CMOS phase invert bit causes the signal on an OUTxN pin to be the opposite of the signal appearing on the OUTxP pin. The drive strength bit allows the user to control whether the output uses weak (0) or strong (1) drive capability (applies to CMOS and LVDS but not LVPECL). For the CMOS family, the strong setting implies normal CMOS drive capability, whereas the weak setting implies low capacitive loading and allows for reduced EMI. For the LVDS family, the weak setting provides 3.5 mA drive current for standard LVDS operation, whereas the strong setting provides 7 mA for double terminated or double voltage LVDS operation. Note that 3.5 mA and 7 mA are the nominal drive current values when using the internal current setting resistor.
Clock Distribution Synchronization
A block diagram of the distribution synchronization functionality appears in Figure 48. The synchronization sequence begins with the primary synchronization signal, which ultimately results in delivery of a synchronization strobe to the clock distribution logic. As indicated, the primary synchronization signal originates from four possible sources. * * Direct sync source via the sync distribution bit (Register 0A02, Bit 1) Automatic sync source based on frequency or phase lock detection as controlled via the automatic synchronization register (Address 0403) Multifunction pin sync source via one of the multifunction pins (M0 to M7) EEPROM sync source via the EEPROM
* *
Output Current Control with an External Resistor
By default, the output drivers have an internal current setting resistor (3.12 k nominal) that establishes the nominal drive current for the LVDS and LVPECL operating modes. Instead of using the internal resistor, the user can set the external distribution resistor bit (Register 0400, Bit 5) and connect an external resistor to the OUT_RSET pin. Note that this feature supports an external resistor value of 3.12 k only, allowing for tighter control of the output current than is possible by using the internal current setting resistor. However, if the user elects to use a nonstandard external resistance, the following equations provide the output drive current as a function of the external resistance (R):
All four sources of the primary synchronization signal are logic OR'd, so any one of them can synchronize the clock distribution output at any time. When using the multifunction pins, the synchronization event is the falling edge of the selected signal. When using the sync distribution bit, the user sets and then clears the bit. The synchronization event is the clearing operation; that is, the Logic 1 to Logic 0 transition of the bit. The primary synchronization signal can synchronize the distribution output directly or it can enable a secondary synchronization signal. This functionality depends on the two sync source bits in the distribution synchronization register (Register 0402, Bits[5:4]). When sync source = 00 (direct), the falling edge of the primary synchronization signal synchronizes the distribution output directly. When sync source = 01, the rising edge of the primary synchronization signal triggers the circuitry that detects a rising edge of the active input reference. The detection of the rising edge is what synchronizes the distribution output. When sync source = 10, the rising edge of the primary synchronization signal triggers the circuitry that detects a rollover of the DDS accumulator (after processing by the DPLL feedback divider). This corresponds to the zero crossing of the output of the phase-to-amplitude converter in the DDS (less the openloop phase offset stored in Register 030D to Register 030E). The detection of the DPLL feedback edge is what synchronizes the distribution output.
I LVDS 0 =
I LVDS1 =
I LVPECL =
10.8325 R
21.665 R
24.76 R
The numeric subscript associated with the LVDS output current corresponds to the logic state of the drive strength bit in the distribution channel modes register (Address 0404 to Address 0407). For R = 3.12 k, the equations yield ILVDS0 = 3.5 mA, ILVDS1 = 7.0 mA, and ILVPECL = 8.0 mA. Note that the device maintains a constant 1.238 V (nominal) across the external resistor.
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AD9548
Active Reference Synchronization (Zero Delay)
Active reference synchronization is the term applied to the case when sync source = 01 (Register 0402, Bits[5:4]). Referring to Figure 48, this means that the active reference sync path is active because Bit 4 = 1, enabling the lower AND gate and disabling the upper AND gate. The edge detector in the active reference sync block monitors the rising edges of the active reference (the mux selects the active reference automatically). The edge detector is armed via the primary synchronization signal, which is one of the four inputs to the OR gate (typically the direct sync source). As soon as the edge detector is armed, its output goes high, which stalls the output dividers in the clock distribution block. Furthermore, once armed, a rising edge from the active reference forces the output of the edge detector low. This restarts the output dividers, thereby synchronizing the clock distribution block. The term zero delay applies because it provides a means to edge align the output signal with the active input reference signal. Typically, zero-delay architectures use the output signal in the
PRIMARY SYNCHRONIZATION SIGNAL DIRECT SYNC AUTOMATIC SYNC SOURCE (REGISTER 0403) EDGE DETECT MULTIFUNCTION PIN SYNC SOURCE DPLL FEEDBACK EDGE ARM EDGE DETECT
feedback loop of a PLL to track input/output edge alignment. Active reference synchronization, however, operates open loop. That is, synchronization of the output via the distribution synchronization logic occurs on a single edge of the active reference. The fact that an active reference edge triggers the falling edge of the synchronization pulse means that the falling edge is asynchronous to the signal that clocks the distribution output dividers (CLKINx). Therefore, the output clock distribution logic reclocks the internal synchronization pulse to synchronize it with the CLKINx signal. This means that the output dividers restart after a deterministic delay associated with the reclocking circuitry. This deterministic delay has two components. The first deterministic delay component is four or five periods of the CLKINx signal. The one period uncertainty is due to the unknown position of the asynchronous reference clock edge relative to the CLKINx signal. The second deterministic delay component is one output period of the distribution divider.
DIRECT SYNC SOURCE (REGISTER 0A02[1])
REGISTER 0402[5]
TO MULTIFUNCTION PIN STATUS LOGIC
0 1 TO CLOCK DISTRIBUTION SYNCHRONIZATION CONTROL STALL DIVIDERS SYNC OUTPUT DISTRIBUTION
SYSCLK/4
EEPROM SYNC SOURCE
DPLL EDGE SYNC
REGISTER 0402[4]
RESET
ARM EDGE DETECT
REF A REF AA
REF D REF DD
08022-023
ACTIVE REFERENCE SYNC
Figure 48. Output Synchronization Block Diagram
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AD9548
The deterministic delay, expressed as tLATENCY in the following equation is a function of the frequency division factor (Qn) of the channel divider associated with the zero-delay channel. tLATENCY = (Qn + 4) x tCLK_IN or tLATENCY = (Qn + 5) x tCLK_IN In addition to deterministic delay, there is random delay (tPROP) associated with the propagation of the reference signal through the input reference receiver, as well as the propagation of the clock signal through the clock distribution logic. The total delay is tDELAY = tLATENCY + tPROP The user can compensate for tDELAY by using the phase offset controls of the device to move the edge timing of the distribution output signal relative to the input reference edge. One method is to use the open-loop phase offset registers (Address 030D to Address 030E) for timing adjustment. However, be sure to use sufficiently small phase increments to make the adjustment. Too large a phase step can result in the clock distribution logic missing a CLKINx edge, thus ruining the edge alignment process. The appropriate phase increment depends on the transient response of any external circuitry connected between the DACOUTx and CLKINx pins. The other method is to use the closed-loop phase offset registers (Address 030F to Address 0315) for timing adjustment. However, be sure to use a sufficiently small phase vs. time profile. Changing the phase too quickly can cause the DPLL to lose lock, thus ruining the edge alignment process. Note that the AD9548 phase slew limit register (Address 0316 to Address 0317) can be used to limit the rate of change of phase automatically, thereby mitigating the potential loss-of-lock problem. To guarantee synchronization of the output dividers, it is important to make any edge timing adjustments after the synchronization event. Furthermore, when making timing adjustments, the distribution outputs can be disabled and then enabled after the adjustment is complete. This prevents the device from generating output clock signals during the timing adjustment process. Note that the form of zero-delay synchronization described here does not track propagation time variations within the distribution clock input path or the reference input path (on or off chip) over temperature, supply, and so on. It is strictly a one-time synchronization event.
Synchronization Mask
Each output channel has dedicated synchronization mask bits (Register 0402, Bits[3:0]). When the mask bit associated with a particular channel is set, then that channel does not respond to the synchronization signal. This allows the device to operate with the masked channels active and the unmasked channels stalled while they wait for a synchronization pulse.
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AD9548 STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M7)
The AD9548 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on the contents of Register 0200 to Register 0207. To monitor an internal function with a multifunction pin, write a Logic 1 to the most significant bit of the register associated with the desired multifunction pin. The value of the seven least significant bits of the register defines the control function, as shown in Table 24.
Table 24. Multifunction Pin Output Functions, Register 0200 to Register 0207 (Bit 7 = 1)
Bits[6:0] Value 0 1 2 3 4 5 6 7 8 9 10 11 12 to 15 16 17 18 19 20 21 22 23 24 25 26 27 to 31 32 33 Output Function Static Logic 0 Static Logic 1 System clock divided by 32 Watchdog timer output EEPROM upload in progress EEPROM download in progress EEPROM fault detected SYSCLK PLL lock detected SYSCLK PLL calibration in progress Unused Unused SYSCLK PLL stable Unused DPLL free running DPLL active DPLL in holdover DPLL in reference switchover Active reference: phase master DPLL phase locked DPLL frequency locked DPLL phase slew limited DPLL frequency clamped Tuning word history available Tuning word history updated Unused Reference A fault Reference AA fault Source Proxy Bits[6:0] Value 34 35 36 37 38 39 40 to 47 48 49 50 51 52 53 54 55 56 to 63 64 65 Register 0D00, Bit 0 66 Register 0D00, Bit 1 67 Register 0D00, Bit 2 Register 0D01, Bit 0 Register 0D01, Bit 1 68 69 70 Register 0D01, Bit 4 Register 0D0A, Bit 0 Register 0D0A, Bit 1 Register 0D0A, Bit 2 Register 0D0A, Bit 3 Register 0D0A, Bit 6 Register 0D0A, Bit 4 Register 0D0A, Bit 5 Register 0D0A, Bit 7 Register 0D0B, Bit 7 Register 0D0B, Bit 6 Register 0D05, Bit 4 71 72 to 79 80 81 to 127 Output Function Reference B fault Reference BB fault Reference C fault Reference CC fault Reference D fault Reference DD fault Unused Reference A valid Reference AA valid Reference B valid Reference BB valid Reference C valid Reference CC valid Reference D valid Reference DD valid Unused Reference A active eference Reference AA active reference Reference B active reference Reference BB active reference Reference C active reference Reference CC active reference Reference D active reference Reference DD active reference Unused Clock distribution sync pulse Unused Source Proxy Register 0D0E, Bit 2 Register 0D0F, Bit 2 Register 0D10, Bit 2 Register 0D11, Bit 2 Register 0D12, Bit 2 Register 0D13, Bit 2 Register 0D0C, Bit 3 Register 0D0D, Bit 3 Register 0D0E, Bit 3 Register 0D0F, Bit 3 Register 0D10, Bit 3 Register 0D11, Bit 3 Register 0D12, Bit 3 Register 0D13, Bit 3 Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0] Register 0D0B, Bits[2:0]
Register 0D03, Bit 3
To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Table 25.
Table 25. Multifunction Pin Input Functions, Register 0200 to Register 0207 (Bit 7 = 0)
Bits[6:0] Value 0 1 2 3 4 Output Function Unused (default) I/O update Full power-down Watchdog reset IRQ reset Destination Proxy Register 0005, Bit 0 Register 0A00, Bit 0 Register 0A03, Bit 0 Register 0A03, Bit 1
Register 0D0C, Bit 2 Register 0D0D, Bit 2
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AD9548
Bits[6:0] Value 5 6 to 15 16 17 18 19 20 21 to 31 32 33 34 35 36 37 38 39 40 to 47 48 49 50 51 52 53 54 55 56 to 63 64 65 66 67 68 69 70 to 127 Output Function Tuning word history reset Unused Holdover Free run Reset incremental phase offset Increment incremental phase offset Decrement incremental phase offset Unused Override Reference Monitor A Override Reference Monitor AA Override Reference Monitor B Override Reference Monitor BB Override Reference Monitor C Override Reference Monitor CC Override Reference Monitor D Override Reference Monitor DD Unused Force validation Timeout A Force validation Timeout AA Force validation Timeout B Force validation Timeout BB Force validation Timeout C Force validation Timeout CC Force validation Timeout D Force validation Timeout DD Unused Enable OUT0 Enable OUT1 Enable OUT2 Enable OUT3 Enable OUT0, OUT1, OUT2, OUT3 Sync clock distribution outputs Unused Destination Proxy Register 0A03, Bit 2 Register 0A01, Bit 6 Register 0A01, Bit 5 Register 0A0C, Bit 2 Register 0A0C, Bit 0 Register 0A0C, Bit 1
If more than one multifunction pin operates on the same control signal, then internal priority logic ensures that only one multifunction pin serves as the signal source. The selected pin is the one with the lowest numeric suffix. For example, if both M3 and M7 operate on the same control signal, then M3 is used as the signal source and the redundant pins are ignored. At power-up, the multifunction pins can be used to force the device into certain configurations as defined in the initial pin programming section. This functionality, however, is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the EEPROM.
Register 0A0F, Bit 0 Register 0A0F, Bit 1 Register 0A0F, Bit 2 Register 0A0F, Bit 3 Register 0A0F, Bit 4 Register 0A0F, Bit 5 Register 0A0F, Bit 6 Register 0A0F, Bit 7
IRQ PIN
The AD9548 has a dedicated interrupt request (IRQ) pin. The IRQ pin output mode register (Register 0208, Bits[1:0]) controls how the IRQ pin asserts an interrupt based on the value of the two bits, as follows: 00--The IRQ pin is high impedance when deasserted and active low when asserted and requires an external pull-up resistor (this is the default operating mode). 01--The IRQ pin is high impedance when deasserted and active high when asserted and requires an external pull-down resistor. 10--The IRQ pin is Logic 0 when deasserted and Logic 1 when asserted. 11--The IRQ pin is Logic 1 when deasserted and Logic 0 when asserted. The AD9548 asserts the IRQ pin whenever any of the bits in the IRQ monitor register (Address 0D02 to Address 0D09) are Logic 1. Each bit in this register is associated with an internal function capable of producing an interrupt. Furthermore, each bit of the IRQ monitor register is the result of a logical AND of the associated internal interrupt signal and the corresponding bit in the IRQ mask register (Address 0209 to Address 0210). That is, the bits in the IRQ mask register have a one-to-one correspondence with the bits in the IRQ monitor register. Whenever an internal function produces an interrupt signal and the associated IRQ mask bit is set, then the corresponding bit in the IRQ monitor register is set. The user should be aware that clearing a bit in the IRQ mask register removes only the mask associated with the internal interrupt signal. It does not clear the corresponding bit in the IRQ monitor register. The IRQ pin is the result of a logical OR of all the IRQ monitor register bits. Thus, the AD9548 asserts the IRQ pin so long as any of the IRQ monitor register bits are Logic 1. Note that it is possible to have multiple bits set in the IRQ monitor register. Therefore, when the AD9548 asserts the IRQ pin, it may indicate an interrupt from several different internal functions. The IRQ monitor register provides the user with a means to interrogate the AD9548 to determine which internal function(s) produced the interrupt.
Register 0A0E, Bit 0 Register 0A0E, Bit 1 Register 0A0E, Bit 2 Register 0A0E, Bit 3 Register 0A0E, Bit 4 Register 0A0E, Bit 5 Register 0A0E, Bit 6 Register 0A0E, Bit 7
Register 0401, Bit 0 Register 0401, Bit 1 Register 0401, Bit 2 Register 0401, Bit 3 Register 0401, Bits[3:0] Register 0A02, Bit 1
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AD9548
Typically, when the AD9548 asserts the IRQ pin, the user interrogates the IRQ monitor register to identify the source of the interrupt request. After servicing an indicated interrupt, the user should clear the associated IRQ monitor register bit via the IRQ clearing register (Address 0A04 to Address 0A0B). The bits in the IRQ clearing register have a one-to-one correspondence with the bits in the IRQ monitor register. Note that the IRQ clearing register is autoclearing. The IRQ pin remains asserted until the user clears all of the bits in the IRQ monitor register that indicate an interrupt. It is also possible to collectively clear all of the IRQ monitor register bits by setting the reset all IRQs bit in the reset function register (Register 0A03, Bit 1). Note that this is an autoclearing bit. Setting this bit results in deassertion of the IRQ pin. Alternatively, the user can program any of the multifunction pins to clear all IRQs. This allows the user to clear all IRQs by means of a hardware pin rather than by a serial I/O port operation.
EEPROM
EEPROM Overview
The AD9548 contains an integrated 2048-byte, electrically erasable, programmable read-only memory (EEPROM). The AD9548 can be configured to perform a download at power-up via the multifunction pins (M3 to M7), but uploads and downloads can also be done on demand via the EEPROM control register (Address 0E00 to Address 0E03). The EEPROM provides the ability to upload and download configuration settings to and from the register map. Figure 49 shows a functional diagram of the EEPROM. Register 0E10 to Register 0E3F represent a 48-byte scratch pad that enables the user to store a sequence of instructions for transferring data to the EEPROM from the device settings portion of the register map. Note that the default values for these registers provide a sample sequence for saving/retrieving all of the AD9548 EEPROM-accessible registers. Figure 49 shows the connectivity between the EEPROM and the controller that manages data transfer between the EEPROM and the register map. The controller oversees the process of transferring EEPROM data to and from the register map. There are two modes of operation handled by the controller: saving data to the EEPROM (upload mode) or retrieving data from the EEPROM (download mode). In either case, the controller relies on a specific instruction set.
M7 M6 M5 M4 M3 DEVICE SETTINGS ADDRESS POINTER DATA EEPROM CONTROLLER EEPROM ADDRESS POINTER
WATCHDOG TIMER
The watchdog timer is a general-purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0211 to Address 0212). A value of 0 in this register disables the timer. A nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms. If enabled, the timer runs continuously and generates a timeout event whenever the timeout period expires. The user has access to the watchdog timer status via the IRQ mechanism and the multifunction pins (M0 to M7). In the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 32 system clock periods. There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first is by writing a Logic 1 to the autoclearing reset watchdog bit in the reset function register (Register 0A03, Bit 0). Alternatively, the user can program any of the multifunction pins to reset the watchdog timer. This allows the user to reset the timer by means of a hardware pin rather than by a serial I/O port operation.
EEPROM (000 TO 7FF)
SCRATCH PAD ADDRESS POINTER
DATA
DEVICE SETTINGS (0100 TO 0A10)
CONDITION (0E01 [4:0])
SCRATCH PAD (0E10 TO 0E3F)
DATA
REGISTER MAP
Figure 49. EEPROM Functional Diagram
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08022-024
SERIAL INPUT/OUTPUT PORT
AD9548
Table 26. EEPROM Controller Instruction Set
Instruction Value (Hex) 00 to 7F Instruction Type Data Bytes Required 3 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that together indicate a starting address in the register map. Encoded in the data instruction is the number of bytes to transfer, which is one more than the instruction value. When the controller encounters this instruction while downloading from the EEPROM, it issues a soft I/O update (see Register 0005 in Table 41). When the controller encounters this instruction while downloading from the EEPROM, it initiates a system clock calibration sequence (see Register 0A02 in Table 120). When the controller encounters this instruction while downloading from the EEPROM, it issues a sync pulse to the output distribution synchronization (see Register 0A02 in Table 120). B1 to CF are condition instructions and correspond to Condition 1 through Condition 31, respectively. B0 is the null condition instruction. See the EEPROM Conditional Processing section for details. When the controller encounters this instruction in the scratch pad while uploading to the EEPROM, it resets the scratch pad address pointer and holds the EEPROM address pointer at its last value. This allows storage of more than one instruction sequence in the EEPROM. Note that the controller does not copy this instruction to the EEPROM during upload. When the controller encounters this instruction in the scratch pad while uploading to the EEPROM, it resets both the scratch pad address pointer and the EEPROM address pointer and then enters an idle state. When the controller encounters this instruction while downloading from the EEPROM, it resets the EEPROM address pointer and then enters an idle state.
80 A0
I/O update Calibrate
1 1
A1
Distribution sync
1
B0 to CF
Condition
1
FE
Pause
1
FF
End
1
EEPROM Instructions
Table 26 lists the EEPROM controller instruction set. The controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which it only recognizes in upload mode. The I/O update, calibrate, distribution sync, and end instructtions are mostly self-explanatory. The others, however, warrant further detail, as described in the following paragraphs. Data instructions are those that have a value from 00 to 7F. A data instruction tells the controller to transfer data between the EEPROM and the register map. The controller needs the following two parameters to carry out the data transfer: * * The number of bytes to transfer The register map target address
Note that, in the EEPROM scratch pad, the two registers that comprise the address portion of a data instruction have the MSB of the address in the D7 position of the lower register address. The bit weight increases left to right, from the lower register address to the higher register address. Furthermore, the starting address always indicates the lowest numbered register map address in the range of bytes to transfer. That is, the controller always starts at the register map target address and counts upward regardless of whether the serial I/O port is operating in I2C, SPI LSB-first, or SPI MSB-first mode. As part of the data transfer process during an EEPROM upload, the controller calculates a 1-byte checksum and stores it as the final byte of the data transfer. As part of the data transfer process during an EEPROM download, however, the controller again calculates a 1-byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. If an upload/download checksum pair does not match, the controller sets the EEPROM fault status bit. If the upload/download checksums match for all data instructions encountered during a download sequence, the controller sets the EEPROM complete status bit. Condition instructions are those that have a value from B0 to CF. Condition instructions B1 to CF represent Condition 1 to Condition 31, respectively. The B0 condition instruction is
The controller decodes the number of bytes to transfer directly from the data instruction itself by adding one to the value of the instruction. For example, the data instruction, 1A, has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). Whenever the controller encounters a data instruction, it knows to read the next two bytes in the scratch pad because these contain the register map target address.
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AD9548
special because it represents the null condition (see the EEPROM Conditional Processing section). A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. This way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence. This process is repeatable until an upload sequence contains an end instruction. The pause instruction is also useful when used in conjunction with condition processing. It allows the EEPROM to contain multiple occurrences of the same register(s), with each occurrence linked to a set of conditions (see the EEPROM Conditional Processing section). controller increments the EEPROM address pointer by one more than the number of bytes transferred. Note that, when the controller transfers data associated with an active register, it actually transfers the buffered contents of the register (see the Buffered/Active Registers section for details on the difference between buffered and active registers). This allows for the transfer of nonzero autoclearing register contents. Note that conditional processing (see the EEPROM Conditional Processing section) does not occur during an upload sequence.
EEPROM Download
An EEPROM download results in data transfer from the EEPROM to the device register map. To download data, the user sets the autoclearing load from EEPROM bit (Register 0E03, Bit 1). This commands the controller to initiate the EEPROM download process. During download, the controller reads the EEPROM data byte by byte, incrementing the EEPROM address pointer as it goes, until it reaches an end instruction. As the controller reads the EEPROM data, it executes the stored instructions, which includes transferring stored data to the device settings portion of the register map whenever it encounters a data instruction. Note that conditional processing (see the EEPROM Conditional Processing section) is only applicable when downloading.
EEPROM Upload
To upload data to the EEPROM, the user must first ensure that the write enable bit (Register 0E00, Bit 0) is set. Then, on setting the autoclearing save to EEPROM bit (Register 0E02, Bit 0), the controller initiates the EEPROM data storage process. Uploading EEPROM data requires that the user first write an instruction sequence into the scratch pad registers. During the upload process, the controller reads the scratch pad data byte by byte, starting at Register 0E10 and incrementing the scratch pad address pointer as it goes until it reaches a pause or End instruction. As the controller reads the scratch pad data, it transfers the data from the scratch pad to the EEPROM (byte by byte) and increments the EEPROM address pointer accordingly, unless it encounters a data instruction. A data instruction tells the controller to transfer data from the device settings portion of the register map to the EEPROM. The number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratch pad. When the controller encounters a data instruction, it stores the instruction in the EEPROM, increments the EEPROM address pointer, decodes the number of bytes to be transferred, and increments the scratch pad address pointer. Then it retrieves the next two bytes from the scratch pad (the target address) and increments the scratch pad address pointer by 2. Next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the EEPROM. When it completes the data transfer, the controller stores an extra byte in the EEPROM to serve as a checksum for the transferred block of data. To account for the checksum byte, the
Automatic EEPROM Download
Following a power-up, an assertion of the RESET pin, or a soft reset (Register 0000, Bit 5 = 1), if FncInit[7:3] 0 (see the Initial Pin Programming section), then the instruction sequence stored in the EEPROM executes automatically with condition = FncInit[7:3]. In this way, a previously stored set of register values downloads automatically on power-up or with a hard or soft reset. See the EEPROM Conditional Processing section for details regarding conditional processing and the way it modifies the download process.
EEPROM Conditional Processing
The condition instructions allow conditional execution of EEPROM instructions during a download sequence. During an upload sequence, however, they are stored as is and have no effect on the upload process. Note that, during EEPROM downloads, the condition instructions themselves and the end instruction always execute unconditionally. Conditional processing makes use of two elements: the condition (from Condition 1 to Condition 31) and the condition tag board. The relationships among the condition, the condition tag board, and the EEPROM controller appear schematically in Figure 50.
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AD9548
CONDITION TAG BOARD 1 2 10 18 26 3 11 19 27 4 12 20 28 5 13 21 29 6 14 22 30 7 15 23 5 24 IF B1 INSTRUCTION CF, THEN TAG DECODED CONDITION 25 31 IF {0E01, BITS[4:0] 0} CONDITION = 0E01, BITS[4:0] ELSE CONDITION = FncInit, BITS[7:3] ENDIF 5 5 REGISTER 0E01, BITS[4:0] FncInit, BITS[7:3]
M7
M3
EXAMPLE
CONDITION 3 AND CONDITION 13 ARE TAGGED
8 16
9 17
EEPROM WATCH FOR OCCURRENCE OF CONDITION INSTRUCTIONS DURING DOWNLOAD.
IF INSTRUCTION = B0, THEN CLEAR ALL TAGS
STORE CONDITION INSTRUCTIONS AS THEY ARE READ FROM THE SCRATCH PAD.
COND ITION
CONDITION HANDLER SCRATCH PAD
EXECUTE/SKIP INSTRUCTION(S)
UPLOAD PROCEDURE
DOWNLOAD PROCEDURE
IF {NO TAGS} OR {CONDITION = 0} EXECUTE INSTRUCTIONS ELSE IF {CONDITION IS TAGGED} EXECUTE INSTRUCTIONS ELSE SKIP INSTRUCTIONS ENDIF ENDIF
EEPROM CONTROLLER
Figure 50. EEPROM Conditional Processing
The condition is a 5-bit value with 32 possibilities. Condition = 0 is the null condition. When the null condition is in effect, the EEPROM controller executes all instructions unconditionally. The remaining 31 possibilities, condition = 1 through condition = 31, modify the EEPROM controller's handling of a download sequence. The condition originates from one of two sources (see Figure 50), as follows: * FncInit, Bits[7:3], which is the state of the M3 to M7 multifunction pins at power-up (see the Initial Pin Programming section) Register 0E01, Bits[4:0]
*
If Register 0E01, Bits[4:0] 0, then the condition is the value stored in Register 0E01, Bits[4:0]; otherwise, the condition is FncInit, Bits[7:3]. Note that a nonzero condition present in Register 0E01, Bits[4:0] takes precedence over FncInit, Bits[7:3]. The condition tag board is a table maintained by the EEPROM controller. When the controller encounters a condition instructtion, it decodes the B1 through CF instructions as condition = 1 through condition = 31, respectively, and tags that particular condition in the condition tag board. However, the B0 condition instruction decodes as the null condition, for which the controller clears the condition tag board, and subsequent download instructions execute unconditionally (until the controller encounters a new condition instruction).
During download, the EEPROM controller executes or skips instructions depending on the value of condition and the contents of the condition tag board. Note, however, that condition instructions and the end instruction always execute unconditionally during download. If condition = 0, then all instructions during download execute unconditionally. If condition 0 and there are any tagged conditions in the condition tag board, then the controller executes instructions only if the condition is tagged. If the condition is not tagged, then the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. Note that the condition tag board allows for multiple conditions to be tagged at any given moment. This conditional processing mechanism enables the user to have one download instruction sequence with many possible outcomes depending on the value of the condition and the order in which the controller encounters condition instructions. Table 27 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most recently executed condition instruction is B0 or no conditional instructions have been processed.
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08022-025
AD9548
Table 27. EEPROM Conditional Processing Example
Instruction 0x08 0x01 0x00 0xB1 0x19 0x04 0x00 0xB2 0xB3 0x07 0x05 0x00 0x0A 0xB0 0x80 0x0A Action Transfer the system clock register contents regardless of the current condition. Tag Condition 1 Transfer the clock distribution register contents only if condition = 1 Tag Condition 2 Tag Condition 3 Transfer the reference input register contents only if condition = 1, 2, or 3 Calibrate the system clock only if condition = 1, 2, or 3 Clear the condition tag board Execute an I/O update regardless of the value of the condition Calibrate the system clock regardless of the value of the condition
Reprogram the device control registers for the next desired setup. Then store a new upload sequence in the EEPROM scratch pad with the following general form: 1. 2. Condition instruction (B0) The next desired condition instruction (B1 to CF, but different than the one used during the previous upload to identify a new setup) Data instructions (to save the register contents) along with any required calibrate and/or I/O update instructions Pause instruction (FE)
3. 4.
With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0E02, Bit 0). Repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the EEPROM scratch pad (Step 1 through Step 4), and executing an EEPROM upload (Register 0E02, Bit 0) until all of the desired setups have been uploaded to the EEPROM. Note that, on the final upload sequence stored in the scratch pad, the pause instruction (FE) must be replaced with an end instruction (FF). To download a specific setup on demand, first store the condition associated with the desired setup in Register 0E01, Bits[4:0]. Then perform an EEPROM download (Register 0E03, Bit 1). Alternatively, to download a specific setup at power-up, apply the required logic levels necessary to encode the desired condition on the M3 to M7 multifunction pins. Then power up the device; an automatic EEPROM download occurs. The condition (as established by the M3 to M7 multifunction pins) guides the download sequence and results in a specific setup. Keep in mind that the number of setups that can be stored in the EEPROM is limited. The EEPROM can hold a total of 2048 bytes. Each nondata instruction requires one byte of storage. Each data instruction, however, requires N + 4 bytes of storage, where N is the number of transferred register bytes and the other four bytes include the data instruction itself (one byte), the target address (two bytes), and the checksum calculated by the EEPROM controller during the upload sequence (one byte).
Storing Multiple Device Setups in EEPROM
Conditional processing makes it possible to create a number of different device setups, store them in EEPROM, and download a specific setup on demand. To do so, first program the device control registers for a specific setup. Then, store an upload sequence in the EEPROM scratch pad with the following general form: 1. 2. 3. Condition instruction (B1 to CF) to identify the setup with a specific condition (1 to 31) Data instructions (to save the register contents) along with any required calibrate and/or I/O update instructions Pause instruction (FE)
With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0E02, Bit 0).
Rev. 0 | Page 50 of 112
AD9548 SERIAL CONTROL PORT
SERIAL CONTROL ARBITER POWER-ON RESET 13-BIT ADDRESS SPACE READ ONLY REGION READ/WRITE REGION MULTIFUNCTION PIN CONTROL LOGIC M7 M6 M5 M4 M3 M2 M1 M0
SCLK/SCL CS/SDA SDIO SDO
SPI IC
2
EEPROM
EEPROM CONTROLLER
400kHz
Figure 51. Serial Port Functional Diagram
The AD9548 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9548 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9548 register map. In SPI mode, single or multiple byte transfers are supported. The SPI port configuration is programmable via Register 0000. This register is integrated into the SPI control logic rather than in the register map and is distinct from the I2C Register 0000. It is also inaccessible to the EEPROM controller. A functional diagram of the serial control port, including its relationship to the EEPROM, appears in Figure 51. Although the AD9548 supports both the SPI and I2C serial port protocols, only one is active following power-up (as determined by the multifunction pins, M0 to M2, during the startup sequence). That is, the only way to change the serial port protocol is to reset the device (or cycle the device power supply). Both protocols use a common set of control pins as shown in Figure 52.
SCLK/SCL SDIO SDO CSB/SDA
2 3 4 5
settings based on the startup logic pattern on the M0 to M2 pins (see Table 28). Note that the four MSBs of the slave address are hardware coded as 1011.
Table 28. Serial Port Mode Selection
M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Serial Port Mode SPI IC (address = 1001001) IC (address = 1001010) IC (address = 1001011) IC (address = 1001100) IC (address = 1001101) IC (address = 1001110) IC (address = 1001111)
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 40 MHz. The SDIO (serial data input/output) pin is a dual-purpose pin and acts as either an input only (unidirectional mode) or as both an input and an output (bidirectional mode). The AD9548 default SPI mode is bidirectional. The SDO (serial data output) pin is useful only in unidirectional I/O mode. It serves as the data output pin for read operations. The CS (chip select) pin is an active low control that gates read and write operations. This pin is internally connected to a 30 k pull-up resistor. When CS is high, the SDO and SDIO pins go into a high impedance state.
AD9548
SERIAL CONTROL PORT
Figure 52. Serial Control Port
SPI/IC PORT SELECTION
Because the AD9548 supports both SPI and I2C protocols, the active serial port protocol depends on the logic state of the three multifunction pins, M0 to M2, at startup. If all three pins are set to Logic 0 at startup, then the SPI protocol is active. Otherwise, the I2C protocol is active with seven different I2C slave address
08022-027
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration
Rev. 0 | Page 51 of 112
08022-026
ANALOG BLOCKS AND DIGITAL CORE
AD9548
and data format features are programmable. By default, the AD9548 uses the bidirectional MSB-first mode. The reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode. Assertion (active low) of the CS pin initiates a write or read operation to the AD9548 SPI port. For data transfers of three bytes or fewer (excluding the instruction word), the device supports the CS stalled high mode (see Table 29). In this mode, the CS pin can be temporarily deasserted on any byte boundary, allowing time for the system controller to process the next byte. CS can be deasserted only on byte boundaries, however. This applies to both the instruction and data portions of the transfer. During stall high periods, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort a transfer midstream, then the state machine must be reset by either completing the transfer or by asserting the CS pin for at least one complete SCLK cycle (but less than eight SCLK cycles). Deasserting the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. In the streaming mode (see Table 29), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented. CS must be deasserted at the end of the last byte transferred, thereby ending the stream mode.
Table 29. Byte Transfer Count
W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 Streaming mode
CS is asserted. Deasserting the CS pin on a nonbyte boundary resets the serial control port. Reserved or blank registers are not skipped over automatically during a write sequence. Therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. Generally, it does not matter what data is written to blank registers, but it is customary to write 0s. Most of the serial port registers are buffered (see the Buffered/Active Registers section for details on the difference between buffered and active registers). Therefore, data written into buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This is accomplished with an I/O update operation, which is performed in one of two ways. One is by writing a Logic 1 to Register 0005, Bit 0 (this bit is self-clearing). The other is to use an external signal via an appropriately programmed multifunction pin. The user can change as many register bits as desired before executing an I/O update. The I/O update operation transfers the buffer register contents to their active register counterparts.
Read
The AD9548 supports the long instruction mode only. If the instruction word indicates a read operation, the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word. N is the number of data bytes read and depends on the W0 and W1 bits of the instruction word. The readback data is valid on the falling edge of SCLK. Blank registers are not skipped over during readback. A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0004, Bit 0.
Communication Cycle--Instruction Plus Data
The SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9548 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the number of bytes in the payload and the starting register address of the first payload byte.
SPI Instruction Word (16 Bits)
The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1 and W0, indicate the number of bytes in the transfer (see Table 29). The final 13 bits are the register address (A12 to A0), which indicates the starting register address of the read/write operation (see Table 31).
SPI MSB-/LSB-First Transfers
The AD9548 instruction word and payload can be MSB first or LSB first. The default for the AD9548 is MSB first. The LSB-first mode can be set by writing a 1 to Register 0000, Bit 6. Immediately after the LSB-first bit is set, subsequent serial control port operations are LSB first. When MSB-first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant payload byte. Subsequent data bytes must follow in order from high address to low address. In MSB-first mode, the serial control port internal
Write
If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9548. Data bits are registered on the rising edge of SCLK. The length of the transfer (1, 2, or 3 bytes or streaming mode) depends on the W0 and W1 bits (see Table 29) in the instruction byte. When not streaming, CS can be deasserted after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when
Rev. 0 | Page 52 of 112
AD9548
address generator decrements for each data byte of the multibyte transfer cycle. When Register 0000, Bit 6 = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant payload byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. For multibyte MSB-first (default) I/O operations, the serial control port register address decrements from the specified starting address toward Address 0000. For multibyte LSB-first I/O operations, the serial control port register address increments from the starting address toward Address 1FFF.
Table 31. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB I15 R/W I14 W1 I13 W0 I12 A12 I11 A11 I10 A10 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
Unused addresses are not skipped during multibyte I/O operations; therefore, the user should write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers.
Table 30. Streaming Mode (No Addresses Are Skipped)
Write Mode LSB First MSB First Address Direction Increment Decrement Stop Sequence 0x0000 ... 0x1FFF 0x1FFF ... 0x0000
CS SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
Figure 53. Serial Control Port Write--MSB First, 16-Bit Instruction, Two Bytes of Data
CS SCLK DON'T CARE SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N - 1) DATA
REGISTER (N - 2) DATA
REGISTER (N - 3) DATA
DON'T CARE
Figure 54. Serial Control Port Read--MSB First, 16-Bit Instruction, Four Bytes of Data
tDS tS
CS
tHI tDH tLO
tCLK
tC
SCLK
DON'T CARE
DON'T CARE
SDIO
Figure 55. Serial Control Port Write--MSB First, 16-Bit Instruction, Timing Measurements
Rev. 0 | Page 53 of 112
08022-031
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
08022-030
SDO DON'T CARE
08022-029
SDIO DON'T CARE
AD9548
CS
SCLK
08022-032
tDV
SDIO SDO DATA BIT N DATA BIT N - 1
Figure 56. Timing Diagram for Serial Control Port Register Read
CS SCLK DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE DON'T CARE
08022-033
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N + 1) DATA
Figure 57. Serial Control Port Write--LSB First, 16-Bit Instruction, Two Bytes of Data
CS
tS
tC
tCLK tHI tDS
SCLK
tLO
tDH
SDIO BIT N BIT N + 1
Figure 58. Serial Control Port Timing--Write
Table 32. Serial Control Port Timing
Parameter tDS tDH tCLK tS tC tHI tLO tDV Description Setup time between data and the rising edge of SCLK Hold time between data and the rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO and SDO (see Figure 56)
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08022-034
AD9548
IC SERIAL PORT OPERATION
The I C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The AD9548 I2C port design is based on the I2C fast mode standard from Philips, so it supports both the 100 kHz standard mode and 400 kHz fast mode. Fast mode imposes a glitch tolerance requirement on the control signals. That is, the input receivers ignore pulses of less than 50 ns duration. The AD9548 I2C port consists of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, the AD9548 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by the AD9548. The AD9548 uses direct 16-bit memory addressing instead of traditional 8-bit memory addressing. The AD9548 allows up to seven unique slave devices to occupy the I2C bus. These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. The device slave address is 1001xxx (the three right bits are determined by the M0 to M2 pins). The four MSBs (1001) are hard-wired, while the three LSBs (xxx, determined by the M0 to M2 pins) are programmable via the power-up state of the multifunction pins (see the Initial Pin Programming section).
2
Table 33. I2C Bus Abbreviation Definitions
Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge Nonacknowledge Write Read
The transfer of data is shown in Figure 59. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCL line is low.
SDA
SCL
Figure 59. Valid Bit Transfer
I2C Bus Characteristics
A summary of the various I2C protocols appears in Table 33.
Start/stop functionality is shown in Figure 60. The start condition is characterized by a high-to-low transition on the SDA line while SCL is high. The start condition is always generated by the master to initialize a data transfer. The stop condition is characterized by a low-to-high transition on the SDA line while SCL is high. The stop condition is always generated by the master to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first.
SDA
SCL S START CONDITION
08022-036
P STOP CONDITION
Figure 60. Start and Stop Conditions
SDA
MSB ACK FROM SLAVE-RECEIVER ACK FROM SLAVE-RECEIVER
08022-037
SCL S
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10 P
Figure 61. Acknowledge Bit
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08022-035
DATA LINE STABLE; DATA VALID
CHANGE OF DATA ALLOWED
AD9548
The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. The nonacknowledge bit (A) is the ninth bit attached to any 8-bit data byte. A nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written to or read from the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers. When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a nonacknowledge bit. By receiving the nonacknowledge bit, the slave device knows the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded.
Data Transfer Process
The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). The format for these commands is described in the Data Transfer Format section
SDA MSB ACK FROM SLAVE-RECEIVER
ACK FROM SLAVE-RECEIVER
SCL
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10
S
P
Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer)
SDA ACK FROM MASTER-RECEIVER NON-ACK FROM MASTER-RECEIVER
08022-039
SCL
1
2
3 TO 7
8
9
1
2
3 TO 7
8
9
10
S
P
Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer)
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08022-038
AD9548
Data Transfer Format
Write byte format--the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S Slave address W A RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Send byte format--the send byte protocol is used to set up the register address for subsequent reads.
S Slave address W A RAM address high byte A RAM address low byte A P
Receive byte format--the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
Read byte format--the combined format of the send byte and the receive byte.
S Slave Address W A RAM Address High Byte A RAM Address Low Byte A Sr Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P
IC Serial Port Timing
SDA
tF
SCL
tLO
tR
tSU; DAT tF
tHD; STA
tSP
tR
tBUF
tHD; STA
S
tHD; DAT
tHI
tSU; STA
tSU; STO
Sr
P
S
Figure 64. IC Serial Port Timing
Table 34. I2C Timing Definitions
Parameter fSCL tBUF tHD; STA tSU; STA tSU; STO tHD; DAT tSU; DAT tLO tHI tR tF tSP Description Serial clock Bus free time between stop and start conditions Repeated hold time start condition Repeated start condition setup time Stop condition setup time Data hold time Date setup time SCL clock low period SCL clock high period Minimum/maximum receive SCL and SDA rise time Minimum/maximum receive SCL and SDA fall time Pulse width of voltage spikes that must be suppressed by the input filter
Rev. 0 | Page 57 of 112
08022-040
AD9548 I/O PROGRAMMING REGISTERS
The register map spans an address range from 0x0000 through 0x0E3F (0 to 3647, decimal). Each address provides access to 1 byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example, Register 0A10). In some cases, a group of addresses collectively define a register (for example, the IRQ mask register consists of Register 0209, Register 020A, Register 020B, Register 020C, Register 020D, Register 020E, Register 020F, and Register 0210). In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the register with the lowest address. The bit weight increases right to left, from the lowest register address to the highest register address. For example, the default value of the incremental phase lock offset step size register (Address 0314 to Address 0315) is the 16-bit hexadecimal number, 0x03E8 (not 0xE803). Note that the EEPROM storage sequence registers (Address 0E10 to Address 0E3F) are an exception to the above convention (see the EEPROM Instructions section). An S or C in the Opt column of the register map identifies a register as an active register (otherwise, it is a buffer register). An S entry means that the I/O update signal to the active register is synchronized with the serial port clock or with an input signal driving one of the multifunction pins. On the other hand, a C entry means that the I/O update signal to the active register is synchronized with a clock signal derived from the internal system clock (fS/32), as shown in Figure 65. When reading back a register that has both buffered and active contents, the user can use Register 0004, Bit 0 to select whether to read back the buffer or active contents. Readback of the active contents occurs when Register 0004, Bit 0 = 0, whereas readback of the buffer contents occurs when Register 0004, Bit 0 = 1. Note that a read-only active register requires an I/O update before reading its contents.
I/O UPDATE FROM MULTIFUNCTION PIN LOGIC EDGE DETECT
fS/32
BUFFERED/ACTIVE REGISTERS
There are two broad categories of registers in the AD9548, buffered and active (see Figure 65). Buffered registers are those that can be written to directly from the serial port. They do not need an I/O update to apply their contents to the internal device functions. In contrast, active registers require an I/O update to transfer data between the buffer registers and the internal device functions. In operation, the user programs as many buffer registers as desired and then issues an I/O update. The I/O update occurs by writing to Register 0005, Bit 0 = 1 (or by the external application of the necessary logic level to one of the multifunction pins previously programmed as an I/O update input). The contents of buffer registers connected directly to the internal device functions affect those functions immediately. The contents of buffer registers that connect to active registers do not affect the internal device functions until the I/O update event occurs.
SERIAL CONTROL PORT
ACTIVE C REGISTERS
CS/SDA SDIO SDO SCLK/SCL
5 3 4 2
TO INTERNAL DEVICE FUNCTIONS
08022-041
BUFFER REGISTERS
Figure 65. Buffered and Active Registers
AUTOCLEAR REGISTERS
An A in the Opt column of the register map identifies an autoclear register. Typically, the active value for an autoclear register takes effect following an I/O update. The bit is cleared by the internal device logic upon completion of the prescribed action.
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ACTIVE S REGISTERS
AD9548
REGISTER ACCESS RESTRICTIONS
Read and write access to the register map may be restricted depending on the register in question, the source and direction of access, and the current state of the device. Each register can be classified into one or more access types. When more than one type applies, the most restrictive condition that applies at the moment is used. Whenever access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. Access to nonexistent registers is handled in the same way as for a denied register. one of these sources can have access to a register at any given time (access is mutually exclusive). Whenever the EEPROM controller is active, either in load or store mode, it has exclusive access to these registers.
Read-Only Access
An R in the Opt column of the register map identifies read-only registers. Access is available at all times, including when the EEPROM controller is active.
Exclusion from EEPROM Access
An E in the Opt column of the register map identifies a register with contents that are inaccessible to the EEPROM. That is, the contents of this type of register cannot be transferred directly to the EEPROM or vice versa. Note that read-only registers (R) are inaccessible to the EEPROM, as well.
Regular Access
Registers with regular access do not fall into any other category. Both read and write access to registers of this type can be from either the serial ports or EEPROM controller. However, only
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AD9548 REGISTER MAP
Table 35.
Addr 0000 0000 0001 0002 0003 0004 Opt E Dup E R R E Name SPI control I2C control Reserved Reserved Readback D7 D6 D4 D3 D2 Serial port control and part identification Soft reset Long Unused instruction Soft reset Unused D5 D1 D0 Def 10 00 01 48 00
UnidirecLSB first/ tional Inc Addr Unused Unused Silicon revision number Device ID Unused
0005 0100
A, E S
I/O update
Unused External loop filter enable Charge pump mode (auto/ man) System clock Charge pump current [2:0] Lock detect timer disable
Read buffer register I/O update Lock detect divider [1:0]
00 18
0101 0102
S S
N-divider [7:0] Unused M-divider reset
M-divider [1:0]
2x frequency multiplier enable
PLL enable
SYSCLK reference select [1:0]
28 45
0103 0104 0105 0106 0107 0108 0200 0201 0202 0203 0204 0205 0206 0207 0208 0209 020A 020B 020C 020D
C C C C C C S S S S S S S S C C C C C C
Nom SYSCLK period System clock stability
Nominal system clock period (femtoseconds) [15:0] [1 ns @ 1 ppm accuracy] Unused Nominal system clock period [20:16] System clock stability period (milliseconds) [15:0] Unused System clock stability period (milliseconds) [19:16] General configuration M0 function [6:0] M1 function [6:0] M2 function [6:0] M3 function [6:0] M4 function [6:0] M5 function [6:0] M6 function [6:0] M7 function [6:0] IRQ pin output mode [1:0] SYSCLK Cal SYSCLK Cal complete started EEPROM EEPROM fault complete Phase Phase unlocked locked Phase slew Phase slew unlimited limited Ref A Ref A fault fault cleared Ref B Ref B fault fault cleared Ref C Ref C fault fault cleared
40 42 0F 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
M0 M1 M2 M3 M4 M5 M6 M7 IRQ pin output mode IRQ mask
M0 in/out M1 in/out M2 in/out M3 in/out M4 in/out M5 in/out M6 in/out M7 in/out Unused Unused Unused Switching Unused Ref AA new profile Ref BB new profile Ref CC new profile
SYSCLK unlocked
SYSCLK locked
Unused Distribution sync Freq unlocked Frequency unclamped Ref A new profile Ref B new profile Ref C new profile
Unused Watchdog timer Freq locked Frequency clamped Ref A validated Ref B validated Ref C validated
Closed
Freerun
Holdover History updated Ref AA fault Ref BB fault Ref CC fault
Ref AA validated Ref BB validated Ref CC validated
020E
C
020F
C
Ref AA fault cleared Ref BB fault cleared Ref CC fault cleared
00
00
Rev. 0 | Page 60 of 112
AD9548
Addr 0210 Opt C Name D7 Ref DD new profile D5 D4 Ref DD Ref DD fault fault cleared Watchdog timer (ms) [15:0] [up to 65.5 sec] D6 Ref DD validated D3 Ref D new profile D2 Ref D validated D1 Ref D fault cleared D0 Ref D fault Def 00
0211 0212 0213 0214
C C S S
Watchdog timer DAC current
DAC full-scale current [7:0] DAC Unused shutdown DPLL Free running frequency tuning word [47:0]
DAC full-scale current [9:8]
00 00 FF 01
0300 0301 0302 0303 0304 0305 0306 0307 0308 0309 030A 030B 030C 030D 030E 030F 0310 0311 0312 0313 0314 0315 0316 0317 0318 0319 031A 031B
C C C C C C A, C C C C C C C C C C C C C C C C C C C C C C
Free running frequency tuning word
Update TW Pull-in range limits
Unused Pull-in range lower limit [23:0]
Update TW
Pull-in range upper limit [23:0]
Open loop phase offset Closed loop phase offset
DDS phase offset word [15:0] Fixed phase lock offset [39:0] (picoseconds; signed)
Incremental phase lock offset step size [15:0] (picoseconds) Phase slew limit History accumulation timer History mode Phase slew rate limit [15:0] (ns/sec) History accumulation timer [23:0] (milliseconds)
Unused
0400
S
Distribution settings Distribution enable Distribution synchronization Automatic synchronization Distribution channel modes
Unused
0401 0402
S S
Unused Unused
Single Persistent sample history fallback Clock distribution output External Receiver OUT3 distribution mode powerresistor down OUT3 enable Sync source [1:0] OUT3 sync mask
Incremental average [2:0]
00 00 00 00 00 00 00 00 00 00 FF FF FF 00 00 00 00 00 00 00 E8 03 00 00 30 75 00 00
OUT2 powerdown OUT2 enable OUT2 sync mask
OUT1 powerdown OUT1 enable OUT1 sync mask
OUT0 powerdown OUT0 enable OUT0 sync mask
00
00 00
0403
C
Unused
Automatic sync mode [1:0] OUT0 CMOS phase invert OUT1 CMOS phase invert OUT0 polarity invert OUT1 polarity invert OUT0 drive strength OUT1 drive strength OUT0 mode
00
0404
S
Unused
03
0405
S
Unused
OUT1 mode
03
Rev. 0 | Page 61 of 112
AD9548
Addr 0406 Opt S Name D7 Unused D6 D5 OUT2 CMOS phase invert OUT3 CMOS phase invert D4 OUT2 polarity invert OUT3 polarity invert D3 OUT2 drive strength OUT3 drive strength D2 D1 OUT2 mode D0 Def 03
0407
S
Unused
OUT3 mode
03
0408 0409 040A 040B 040C 040D 040E 040F 0410 0411 0412 0413 0414 0415 0416 0417 0500
S S S S S S S S S S S S S S S S S
Distribution channel dividers
Q0 [23:0]
Unused Q1 [23:0]
Q0 [29:24]
Unused Q2 [23:0]
Q1 [29:24]
Unused Q3 [23:0]
Q2 [29:24]
Unused Reference power-down Reference logic family Manual reference profile selection
Q3 [29:24]
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0501 0502 0503
S S C
0504
C
0505
C
0506
C
0507
C
Phase buildout switching Priorities Reference period
Reference inputs Ref A Ref AA Ref B Ref BB Ref C Ref CC Ref D Ref DD powerpowerpowerpowerpowerpowerpowerpowerdown down down down down down down down Ref BB logic family [1:0] Ref B logic family [1:0] Ref AA logic family [1:0] Ref A logic family [1:0] Ref DD logic family [1:0] Ref D logic family [1:0] Ref CC Logic Family [1:0] Ref C Logic Family [1:0] Ref A manual profile [2:0] Ref AA manual profile [2:0] Enable Ref Enable Ref A manual AA manual profile profile Enable Ref Ref BB manual profile [2:0] Enable Ref Ref B manual profile [2:0] BB Manual B manual Profile profile Enable Ref Ref CC manual profile [2:0] Enable Ref Ref C manual profile [2:0] CC Manual C manual Profile profile Enable Ref Ref DD manual profile [2:0] Enable Ref Ref D manual profile [2:0] DD Manual D manual Profile profile Unused Phase master threshold priority [2:0] Profile 0 Unused Promoted priority [2:0] Nominal period (femtoseconds) [47:0] (up to 1.125 sec)
00 00 00
00
00
00
00
0600 0601 0602 0603 0604 0605 0606 0607 0608 0609 060A 060B 060C 060D 060E
Selection priority [2:0]
Tolerance
Unused Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) Unused Inner tolerance [19:16] Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) Unused Validation timer (milliseconds) [15:0] (up to 65.5 sec)
Rev. 0 | Page 62 of 112
Nominal period [49:48]
Outer tolerance [19:16]
Validation
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
AD9548
Addr 060F 0610 0611 0612 0613 0614 0615 Opt Name Redetect timeout Digital loop filter coefficients D7 D6 D5 D4 D3 D2 D1 D0 Def 00 00 00 00 00 00 00
Redetect timer (milliseconds) [15:0] [up to 65.5 seconds] Alpha-0 linear [15:0]
Alpha-2 exponent [1:0] Beta-0 linear [6:0]
Alpha-1 exponent [5:0] Alpha-2 exponent [2] Beta-0 linear [16:15]
0616 0617 0618 0619 061A 061B 061C
Beta-0 linear [14:7] Unused Beta-1 exponent [4:0] Gamma-0 linear [15:0] Unused Gamma-1 exponent [4:0]
Gamma-0 linear [16]
00 00 00 00 00 00 00
061D 061E 061F 0620 0621 0622 0623 0624 0625 0626 0627 0628 0629 062A 062B 062C 062D 062E 062F 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 063A 063B 063C 06CD 063E 063F 0640 0641
Frequency multiplication
Delta-0 linear [7:0] Delta-0 linear [14:8] Delta-1 exponent [0] Alpha-3 exponent [3:0] R [23:0]
Delta-1 exponent [4:1]
Unused S [23:0]
R [29:24]
Lock detectors
Unused S [29:24] V [7:0] U [3:0] Unused U [9:4] Phase lock threshold (picoseconds) [15:0] Phase lock fill rate [7:0] Phase lock drain rate [7:0] Frequency lock threshold (picoseconds) [23:0]
Unused
V [9:8]
Frequency lock fill rate [7:0] Frequency lock drain rate [7:0] Priorities Reference period Profile 1 Unused Promoted priority [2:0] Nominal period (femtoseconds) [47:0] (up to 1.125 sec) Selection priority [2:0]
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Tolerance
Unused Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) Unused Inner tolerance [19:16] Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) Unused Validation timer (milliseconds) [15:0] (up to 65.5 sec)
Rev. 0 | Page 63 of 112
Nominal period [49:48]
Outer tolerance [19:16]
Validation
AD9548
Addr 0642 0643 0644 0645 0646 0647 Opt Name Redetect timeout Digital loop filter coefficients D7 D6 D5 D4 Redetect timer (milliseconds) [15:0] (up to 65.5 sec) Alpha-0 linear [15:0] Alpha-2 exponent [1:0] Beta-0 linear [6:0] Alpha-1 exponent [5:0] Alpha-2 exponent [2] Beta-0 linear [16:15] D3 D2 D1 D0 Def 00 00 00 00 00 00
0648 0649 064A 064B 064C 064D 064E 064F 0650 0651 0652 0653 0654 0655 0656 0657 0658 0659 065A 065B 065C 065D 065E 065F 0660 0661 0662 0663 0664 to 067F 0680 0681 0682 0683 0684 0685 0686 0687 0688 0689 068A 068B 068C 068D 068E 068F
Beta-0 linear [14:7] Unused Beta-1 exponent [4:0] Gamma-0 linear [15:0] Unused Gamma-1 exponent [4:0]
Gamma-0 linear [16]
00 00 00 00 00 00 00
Frequency multiplication
Delta-0 linear [7:0] Delta-1 exDelta-0 linear [14:8] ponent [0] Alpha-3 exponent [3:0] R [23:0]
Delta-1 exponent [4:1]
Unused S [23:0]
R [29:24]
Lock detectors
Unused S [29:24] V [7:0] U [3:0] Unused U [9:4] Phase lock threshold (picoseconds) [15:0] Phase lock fill rate [7:0] Phase lock drain rate [7:0] Frequency lock threshold (picoseconds) [23:0]
Unused
V [9:8]
Frequency lock fill rate [7:0] Frequency lock drain rate [7:0] Unused
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Priorities Reference period
Profile 2 Unused Promoted priority [2:0] Nominal period (femtoseconds) [47:0] (up to 1.125 sec)
Selection priority [2:0]
Tolerance
Unused Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) Unused Inner tolerance [19:16] Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) Unused Validation timer (milliseconds) [15:0] (up to 65.5 sec)
Rev. 0 | Page 64 of 112
Nominal period [49:48]
Outer tolerance [19:16]
Validation
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
AD9548
Addr 0690 0691 0692 0693 0694 0695 Opt Name Redetect timeout Digital loop filter coefficients D7 D6 D5 D4 D3 Redetect timer (milliseconds) [15:0] (up to 65.5 seconds) Alpha-0 linear [15:0] Alpha-2 exponent [1:0] Beta-0 linear [6:0] Alpha-1 exponent [5:0] Alpha-2 exponent [2] Beta-0 linear [16:15] D2 D1 D0 Def 00 00 00 00 00 00
0696 0697 0698 0699 069A 069B 069C
Beta-0 linear [14:7] Unused Beta-1 exponent [4:0] Gamma-0 linear [15:0] Unused Gamma-1 exponent [4:0]
Gamma-0 linear [16]
00 00 00 00 00 00 00
069D 069E 069F 06A0 06A1 06A2 06A3 06A4 06A5 06A6 06A7 06A8 06A9 06AA 06AB 06AC 06AD 06AE 06AF 06B0 06B1 06B2 06B3 06B4 06B5 06B6 06B7 06B8 06B9 06BA 06BB 06BC 06BD 06BE 06BF
Frequency multiplication
Delta-0 linear [7:0] Delta-1 Delta-0 linear [14:8] exponent [0] Alpha-3 exponent [3:0] R [23:0]
Delta-1 exponent [4:1]
Unused S [23:0]
R [29:24]
Lock detectors
Unused S [29:24] V [7:0] U [3:0] Unused U [9:4] Phase lock threshold (picoseconds) [15:0] Phase lock fill rate [7:0] Phase lock drain rate [7:0] Frequency lock threshold (picoseconds) [23:0]
Unused
V [9:8]
Frequency lock fill rate [7:0] Frequency lock drain rate [7:0] Priorities Reference period Profile 3 Unused Promoted priority [2:0] Nominal period (femtoseconds) [47:0] (up to 1.125 sec) Selection priority [2:0]
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Tolerance
Unused Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) Unused Inner tolerance [19:16] Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) Unused Outer tolerance [19:16]
Nominal period [49:48]
Rev. 0 | Page 65 of 112
AD9548
Addr 06C0 06C1 06C2 06C3 06C4 06C5 06C6 06C7 Opt Name Validation Redetect timeout Digital loop filter coefficients D7 D6 D5 D4 Validation timer (milliseconds) [15:0] (up to 65.5 sec) Redetect timer (milliseconds) [15:0] (up to 65.5 sec) Alpha-0 linear [15:0] Alpha-2 exponent [1:0] Beta-0 linear [6:0] Alpha-1 exponent [5:0] Alpha-2 exponent [2] Beta-0 linear [16:15] 00 D3 D2 D1 D0 Def 00 00 00 00 00 00 00 00
06C8 06C9
Beta-0 linear [14:7] Unused Beta-1 exponent [4:0]
00
06CA 06CB 06CC 06CD 06CE
Gamma-0 linear [15:0] Unused Gamma-1 exponent [4:0] Gamma-0 linear [16]
00 00 00 00 00
06CF 06D0 06D1 06D2 06D3 06D4 06D5 06D6 06D7 06D8 06D9 06DA 06DB 06DC 06DD 06DE 06DF 06E0 06E1 06E2 06E3 06E406FF 070007FF
Frequency multiplication
Delta-0 linear [7:0] Delta-0 linear [14:8] Delta-1 exponent [0] Alpha-3 exponent [3:0] R [23:0]
Delta-1 exponent [4:1]
Unused S [23:0]
R [29:24]
Lock detectors
Unused S [29:24] V [7:0] U [3:0] Unused U [9:4] Phase lock threshold (picoseconds) [15:0] Phase lock fill rate [7:0] Phase lock drain rate [7:0] Frequency lock threshold (picoseconds) [23:0]
Unused
V [9:8]
Frequency lock fill rate [7:0] Frequency lock drain rate [7:0] Unused Profile 4 through Profile 7 The functionality of the Profile 4 through Profile 7 address locations (Address 0700 to Address 07FF) is identical to that of the Profile 0 through Profile 3 address locations (Address 0600 to Address 06FF). Operational controls TDC Reference powerpowerdown down User selection mode [1:0]
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Profile 4 through Profile 7 S General power-down Loop mode Cal/sync
0A00
Reset Sans regmap Unused Unused
Unused
0A01 0A02
C S
User holdover
SYSCLK powerdown User freerun
Full Dist DAC powerpowerpowerdown down down User reference selection [2:0] Sync distribution Calibrate system clock
00
00 00
Rev. 0 | Page 66 of 112
AD9548
Addr 0A03 Opt A, C Name ResetFunc D7 Unused D6 Clear LF D5 Clear CCI D4 Clear phase accumulator SYSCLK locked D3 Reset auto sync Unused Distribution sync Freq unlocked Freq unclamped Ref A new profile Ref B new profile Ref C new profile Ref D new profile D2 Reset TW history Unused Watchdog timer Freq locked Freq clamped Ref A validated Ref B validated Ref C validated Ref D validated Reset phase offset Detect B Force Timeout B Ref Mon Override B Ref Mon Bypass B D1 Reset all IRQs SYSCLK Cal complete EEPROM fault Phase unlocked Phase slew unlimited Ref A fault cleared Ref B fault cleared Ref C fault cleared Ref D fault cleared Decrement phase offset Detect AA Force Timeout AA Ref Mon Override AA Ref Mon Bypass AA D0 Reset watchdog SYSCLK Cal started EEPROM complete Phase locked Phase slew limited Ref A fault Ref B fault Ref C fault Ref D fault Increment phase offset Detect A Force Timeout A Ref Mon Override A Ref Mon Bypass A Def 00
0A04 0A05 0A06 0A07 0A08
A, C A, C A, C A, C A, C
IRQ clearing
Unused Unused Switching Unused Ref AA new profile Ref BB new profile Ref CC new profile Ref DD new profile Ref AA validated Ref BB validated Ref CC validated Ref DD validated Closed
SYSCLK unlocked
00 00 00 00 00
Freerun
Holdover History updated Ref AA fault Ref BB fault Ref CC fault Ref DD fault
0A09
A, C
0A0A
A, C
0A0B
A, C
Ref AA fault cleared Ref BB fault cleared Ref CC fault cleared Ref DD fault cleared
00
00
00
0A0C
A, C
Incremental phase offset Reference profile detect Force validation timeout Reference monitor override Reference monitor bypass EEPROM System clock IRQ monitor
Unused
00
0A0D 0A0E
A, C A, C
Detect DD Force Timeout DD Ref Mon Override DD Ref Mon Bypass DD
Detect D Force Timeout D Ref Mon Override D Ref Mon Bypass D
Detect CC Force Timeout CC Ref Mon Override CC Ref Mon Bypass CC
Detect C Force Timeout C Ref Mon Override C Ref Mon Bypass C
Detect BB Force Timeout BB Ref Mon Override BB Ref Mon Bypass BB
00 00
0A0F
C
00
0A10
C
00
0D00 0D01 0D02 0D03 0D04 0D05 0D06
R R R R R R R
Unused Unused Unused Unused Switching Unused Ref AA new profile Ref BB new profile Ref CC new profile Ref DD new profile Ref AA validated Ref BB validated Ref CC validated Ref DD validated Phase build-out History Closed
0D07
R
0D08
R
0D09
R
0D0A 0D0B
R, C R, C
DPLL status
Offset slew limiting Frequency
Status (read only; accessible during EEPROM transactions) Fault Load in detected progress Stable Unused Unused Cal in progress SYSCLK SYSCLK Unused Unused SYSCLK Cal unlocked locked complete DistribuWatchdog EEPROM tion sync timer fault Freerun Holdover Freq Freq Phase unlocked locked unlocked History Freq unFreq Phase slew updated clamped clamped unlimited Ref AA Ref AA Ref A Ref A Ref A fault fault new validated fault cleared profile cleared Ref BB Ref BB Ref B Ref B Ref B fault fault new validated fault cleared profile cleared Ref CC Ref CC Ref C new Ref C Ref C fault fault profile validated fault cleared cleared Ref DD Ref DD Ref D new Ref D Ref D fault fault profile validated fault cleared cleared Freq lock Phase lock Loop Holdover Active switching Active reference priority [3:0] Active reference [3:0]
Rev. 0 | Page 67 of 112
Save in progress Lock detected SYSCLK Cal started EEPROM complete Phase locked Phase slew limited Ref A fault Ref B fault Ref C fault Ref D fault Free running
AD9548
Addr 0D0C 0D0D 0D0E 0D0F 0D10 0D11 0D12 0D13 0D14 0D15 0D16 0D17 0D18 0D19 0E00 0E01 0E02 0E03 E A, E A, E Opt R, C R, C R, C R, C R, C R, C R. C R, C R, C R, C R, C R, C R, C R, C Name Ref A Ref AA Ref B Ref BB Ref C Ref CC Ref D Ref DD Holdover history D7 D6 D5 clamped available Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Profile Selected profile [2:0] selected Tuning word readback [47:0] D4 D3 Valid Valid Valid Valid Valid Valid Valid Valid D2 Fault Fault Fault Fault Fault Fault Fault Fault D1 Fast Fast Fast Fast Fast Fast Fast Fast D0 Slow Slow Slow Slow Slow Slow Slow Slow Def
Nonvolatile memory (EEPROM) control Write protect Condition Save Load Unused Unused Unused Unused EEPROM storage sequence 0E10 0E11 0E12 0E13 0E14 0E15 0E16 0E17 0E18 0E19 0E1A 0E1B 0E1C 0E1D 0E1E 0E1F 0E20 0E21 0E22 0E23 0E24 E E E E E E E E E E E E E E E E E E E E E System clock I/O update SYSCLK calibrate General Data: 9 bytes Address: 0x0100 Action: IO_Update Action: calibrate system clock Data: 21 bytes Address: 0x0200 Data: 28 bytes Address: 0x0300 Data: 26 bytes Address: 0x0400 Action: IO_Update Data: 8 bytes Address: 0x0500 Data: 100 bytes Address: 0x0600 08 01 00 80 A0 14 02 00 1B 03 00 19 04 00 80 07 05 00 63 06 00 Condition value [4:0] Save to EEPROM Unused Half rate mode Write enable 00 00 00 00
Load from EEPROM
DPLL
Clock distribution I/O update Reference inputs Profile 0 and Profile 1
Rev. 0 | Page 68 of 112
AD9548
Addr 0E25 0E26 0E27 0E28 0E29 0E2A 0E2B 0E2C 0E2D 0E2E 0E2F 0E30 0E31 0E32 0E33 0E34 to 0E3F Opt E E E E E E E E E E E E E E E E Name Profile 2 and Profile 3 Profile 4 and Profile 5 Profile 6 and Profile 7 I/O update Operational controls I/O update End of data D7 D6 Data: 100 bytes Address: 0x0680 Data: 100 bytes Address: 0x0700 Data: 100 bytes Address: 0x0780 Action: IO_Update Data: 17 bytes Address: 0x0A00 Action: IO_Update Action: end of data Continuation of scratch pad area D5 D4 D3 D2 D1 D0 Def 63 06 80 63 07 00 63 07 80 80 10 0A 00 80 FF
Rev. 0 | Page 69 of 112
AD9548 REGISTER MAP BIT DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0000 TO REGISTER 0005)
Table 36. Serial Configuration
Address 0000 Bits [7] Bit Name Unidirectional Description Select SPI port SDO pin operating mode. 0 (default) = 3-wire. 1 = 4-wire (SDO pin enabled). Bit order for SPI port. 0 (default) = most significant bit and byte first. 1 = least significant bit and byte first. Device reset (invokes an EEPROM download if M[7:3] 0). 0 (default) = normal operation. 1 = reset. 16-bit mode (the only mode supported by the device). This bit is read only and reads back as Logic 1.
[6]
LSB first
[5]
Soft reset
[4] [0]
Long instruction Unused
Table 37. Reserved Register
Address 0001 Bits [7:0] Bit Name Unused Description
Table 38. Silicon Revision Level (Read-Only)
Address 0002 Bits [7:0] Bit Name Reserved Description Default = 0x01 = 0b00000001
Table 39. Device ID (Read Only)
Address 0003 Bits [7:0] Bit Name Reserved Description Default = 0x48 = 0b01001000
Table 40. Register Readback Control
Address 0004 Bits [7:1] 0 Bit Name Unused Read buffer register Description For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. 0 (default) = reads values currently applied to the internal logic of the device. 1 = reads buffered values that take effect on the next assertion of the I/O update.
Table 41. Soft I/O Update
Address 0005 Bits [7:1] 0 Bit Name Unused I/O update Description Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal control registers of the device. This is an autoclearing bit.
Rev. 0 | Page 70 of 112
AD9548
SYSTEM CLOCK (REGISTER 0100 TO REGISTER 0108)
Table 42. Charge Pump and Lock Detect Control
Address 0100 Bits [7] Bit Name External loop filter enable Charge pump mode Description Enables use of an external SYSCLK PLL loop filter 0 (default) = internal loop filter 1 = external loop filter Charge pump current control 0 (default) = automatic 1 = manual Selects charge pump current when Bit 6 = 1 000 = 125 A 001 = 250 A 010 = 375 A 011 (default) = 500 A 100 = 625 A 101 = 750 A 110 = 875 A 111 = 1000 A Enable the SYSCLK PLL lock detect timer 0 (default) = enable 1 = disable Select lock detect timer depth 00 (default) = 128 01 = 256 10 = 512 11 = 1024
[6]
[5:3]
Charge pump current
[2]
Lock detect timer disable Lock detect timer
[1:0]
Table 43. N Divider
Address 0101 Bits [7:0] Bit Name N-divider Description System clock PLL feedback divider value: 6 N 255 (default = 0x28 = 40)
Table 44. SYSCLK Input Options
Address 0102 Bits [7] [6] Bit Name Unused M-divider reset Description Reset the M-divider 0 = normal operation 1 (default) = reset When not using the M-divider, program this bit to Logic 1. System clock input divider 00 (default) = 1 01 = 2 10 = 4 11 = 8 Enable the 2x frequency multiplier 0 (default) = disable 1 = enable Enable the SYSCLK PLL 0 = disable 1 (default) = enable Input mode select for SYSCLKx pins 00 = crystal resonator 01 (default) = low frequency clock source 10 = high frequency (direct) clock source 11 = input receiver power-down
[5:4]
M-divider
[3]
2x frequency multiplier enable PLL enable
[2]
[1:0]
System clock source
Rev. 0 | Page 71 of 112
AD9548
Table 45. Nominal System Clock (SYSCLK) Period 1
Address 0103 0104 0105 Bits [7:0] [7:0] [7:5] [4:0] Bit Name System clock period (expressed in femtoseconds) Description System clock period, Bits[7:0] System clock period, Bits[15:8]
Unused System clock period
System clock period, Bits[20:16]
1
Units are femtoseconds. The default value is 0x0F424 = 1,000,000 (1 ns) and implies a system clock frequency of 1 GHz.
Table 46. System Clock Stability Period 1
Address 0106 0107 0108 Bits [7:0] [7:0] [7:4] [3:0] Bit Name System clock stability period Unused System clock stability period Description System clock stability period, Bits[7:0] (default = 0x01) System clock stability period, Bits[15:8] (default = 0x00) System clock stability period, Bits[19:16] (default = 0x0) (default period = 0x00001, or 1 ms)
1
Units are milliseconds. The default value is 0x000001 = 1 (1 ms).
GENERAL CONFIGURATION (REGISTER 0200 TO REGISTER 0214)
Register 0200 to Register 0207--Multifunction Pin Control (M0 to M7)
Table 47. Multifunction Pin (M0 to M7) Control 1
Address 0200 Bits [7] Bit Name M0 in/out Description In/out control for the M0 pin 0 (default) = input (control pin) 1 = output (status pin) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M1 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M2 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M3 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M4 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M5 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M6 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000) In/out control for the M7 pin (same as M0) See Table 24 and Table 25 (default = 0xb0000000)
0201 0202 0203 0204 0205 0206 0207
[6:0] [7] [6:0] [7] [6:0] [7] [6:0] [7] [6:0] [7] [6:0] [7] [6:0] [7] [6:0]
M0 function M1 in/out M1 function M2 in/out M2 function M3 in/out M3 function M4 in/out M4 function M5 in/out M5 function M6 in/out M6 function M7 in/out M7 function
1
The default setting for all the multifunction pins is as an unused control input pin.
Table 48. IRQ Pin Output Mode
Address 0208 Bits [7:2] [1:0] Bit Name Unused IRQ pin output mode Description Select the output mode of the IRQ pin 00 (default) = NMOS, open drain (requires an external pull-up resistor) 01 = PMOS, open drain (requires an external pull-down resistor) 10 = CMOS, active high 11 = CMOS, active low
Rev. 0 | Page 72 of 112
AD9548
Register 0209 to Register 0210--IRQ Mask
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0D02 to Address 0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 49. IRQ Mask for SYSCLK
Address 0209 Bits [7:6] [5] [4] [3:2] [1] [0] Bit Name Unused SYSCLK unlocked SYSCLK locked Unused SYSCLK Cal complete SYSCLK Cal started Description Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked Enables IRQ for indicating that SYSCLK calibration has completed Enables IRQ for indicating that SYSCLK calibration has begun
Table 50. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address 020A Bits [7:4] [3] [2] [1] [0] Bit Name Unused Distribution sync Watchdog timer EEPROM fault EEPROM complete Description Enables IRQ for indicating a distribution sync event Enables IRQ for indicating expiration of the watchdog timer Enables IRQ for indicating a fault during an EEPROM load or save operation Enables IRQ for indicating successful completion of an EEPROM load or save operation
Table 51. IRQ Mask for the Digital PLL
Address 020B Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Switching Closed Freerun Holdover Freq unlocked Freq locked Phase unlocked Phase locked Description Enables IRQ for indicating that the DPLL is switching to a new reference Enables IRQ for indicating that the DPLL has entered closed-loop operation Enables IRQ for indicating that the DPLL has entered free-run mode Enables IRQ for indicating that the DPLL has entered holdover mode Enables IRQ for indicating that the DPLL lost frequency lock Enables IRQ for indicating that the DPLL has acquired frequency lock Enables IRQ for indicating that the DPLL lost phase lock Enables IRQ for indicating that the DPLL has acquired phase lock
Table 52. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit
Address 020C Bits [7:5] [4] [3] [2] [1] [0] Bit Name Unused History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Enables IRQ for indicating the occurrence of a tuning word history update Enables IRQ for indicating a state transition frequency limiter from clamped to unclamped Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not slew limiting Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to slew limiting
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Table 53. IRQ Mask for Reference Inputs
Address 020D Bits [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Ref AA new profile Ref AA validated Ref AA fault cleared Ref AA fault Ref A new profile Ref A validated Ref A fault cleared Ref A fault Ref BB new profile Ref BB validated Ref BB fault cleared Ref BB fault Ref B new profile Ref B validated Ref B fault cleared Ref B fault Ref CC new profile Ref CC validated Ref CC fault cleared Ref CC fault Ref C new profile Ref C validated Ref C fault cleared Ref C fault Ref DD new profile Ref DD validated Ref DD fault cleared Ref DD fault Ref D new profile Ref D validated Ref D fault cleared Ref D fault Description Enables IRQ for indicating that Ref AA has switched to a new profile Enables IRQ for indicating that Ref AA has been validated Enables IRQ for indicating that Ref AA has been cleared of a previous fault Enables IRQ for indicating that Ref AA has been faulted Enables IRQ for indicating that Ref A has switched to a new profile Enables IRQ for indicating that Ref A has been validated Enables IRQ for indicating that Ref A has been cleared of a previous fault Enables IRQ for indicating that Ref A has been faulted Enables IRQ for indicating that Ref BB has switched to a new profile Enables IRQ for indicating that Ref BB has been validated Enables IRQ for indicating that Ref BB has been cleared of a previous fault Enables IRQ for indicating that Ref BB has been faulted Enables IRQ for indicating that Ref B has switched to a new profile Enables IRQ for indicating that Ref B has been validated Enables IRQ for indicating that Ref B has been cleared of a previous fault Enables IRQ for indicating that Ref B has been faulted Enables IRQ for indicating that Ref CC has switched to a new profile Enables IRQ for indicating that Ref CC has been validated Enables IRQ for indicating that Ref CC has been cleared of a previous fault Enables IRQ for indicating that Ref CC has been faulted Enables IRQ for indicating that Ref C has switched to a new profile Enables IRQ for indicating that Ref C has been validated Enables IRQ for indicating that Ref C has been cleared of a previous fault Enables IRQ for indicating that Ref C has been faulted Enables IRQ for indicating that Ref DD has switched to a new profile Enables IRQ for indicating that Ref DD has been validated Enables IRQ for indicating that Ref DD has been cleared of a previous fault Enables IRQ for indicating that Ref DD has been faulted Enables IRQ for indicating that Ref D has switched to a new profile Enables IRQ for indicating that Ref D has been validated Enables IRQ for indicating that Ref D has been cleared of a previous fault Enables IRQ for indicating that Ref D has been faulted
020E
020F
0210
Table 54. Watchdog Timer 1
Address 0211 0212
1
Bits [7:0] [7:0]
Bit Name Watchdog timer
Description Watchdog timer, Bits[7:0] (default = 0x00) Watchdog timer, Bits[15:8] (default = 0x00)
The watchdog timer is expressed in milliseconds. The default value is 0 (disabled).
Table 55. Auxiliary DAC 1
Address 0213 Bits [7:0] [7] Bit Name Full-scale current DAC shutdown Description Full scale current, Bits[7:0] (default = 0xFF) Shut down the DAC current sources. 0 (default) = normal operation 1 = shut down Full-scale current, Bits[9:8] (default = 0b01) (default current = 0x1FF, or 20.1 mA)
0214
[6:2] [1:0]
Unused Full-scale current
1
The default DAC full-scale current value is 0x01FF = 511, which equates to 20.1375 mA.
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DPLL CONFIGURATION (REGISTER 0300 TO REGISTER 031B)
Table 56. Free Running Frequency Tuning Word 1
Address 0300 0301 0302 0303 0304 0305
1
Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Bit Name Frequency (expressed as a 48-bit frequency tuning word)
Description Free running frequency tuning word, Bits[7:0] Free running frequency tuning word, Bits[15:8] Free running frequency tuning word, Bits[23:9] Free running frequency tuning word, Bits[31:24] Free running frequency tuning word, Bits[39:32] Free running frequency tuning word, Bits[47:40]
The default free running tuning word is 0x000000 = 0, which equates to 0 Hz.
Table 57. Update TW
Address 0306 Bits [7:1] [0] Bit Name Unused Update TW Description A Logic 1 written to this bit transfers the free running frequency tuning word (Register 0300 to Register 0305) to the register imbedded in the tuning word processing logic. Note that it is not necessary to write the update TW bit when the device is in free-run mode. This is an autoclearing bit.
Table 58. Pull-In Range Lower Limit 1
Address 0307 0308 0309 030A 030B 030C
1
Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Bit Name Pull-in range lower limit (expressed as a 24-bit frequency tuning word)
Description Lower limit pull-in range, Bits[7:0] Lower limit pull-in range, Bits[15:8] Lower limit pull-in range, Bits[23:9]
Pull-in range upper limit (expressed as a 24-bit frequency tuning word)
Upper limit pull-in range, Bits[7:0] Upper limit pull-in range, Bits[15:8] Upper limit pull-in range, Bits[23:9]
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
Table 59. DDS Phase Offset 1
Address 030D 030E Bits [7:0] [7:0] Bit Name Open-loop phase offset (expressed in /215 radians) Description DDS phase offset, Bits[7:0] DDS phase offset, Bits[15:8]
1
The default DDS phase offset is 0.
Table 60. Fixed Closed-Loop Phase Lock Offset 1
Address 030F 0310 0311 0312 0313
1
Bits [7:0] [7:0] [7:0] [7:0] [7:0]
Bit Name Fixed phase lock offset (expressed in picoseconds)
Description Fixed phase lock offset, Bits[7:0] Fixed phase lock offset, Bits[15:8] Fixed phase lock offset, Bits[23:16] Fixed phase lock offset, Bits[31:24] Fixed phase lock offset, Bits[39:32]
The default fixed closed loop phase lock offset is 0.
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Table 61. Incremental Closed-Loop Phase Lock Offset Step Size 1
Address 0314 Bits [7:0] Bit Name Incremental phase lock offset step size (expressed in picoseconds per step) Description Incremental phase lock offset step size, Bits[7:0]
0315
[7:0]
Incremental phase lock offset step size, Bits[15:8]
1
The default incremental closed-loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).
Table 62. Phase Slew Rate Limit 1
Address 0316 0317 Bits [7:0] [7:0] Bit Name Phase slew limit (expressed in nanoseconds per second) Description Phase slew rate limit, Bits[7:0] Phase slew rate limit, Bits[15:8]
1
The default phase slew rate limit is 0 (or disabled).
Table 63. History Accumulation Timer 1
Address 0318 0319 031A
1
Bits [7:0] [7:0] [7:0]
Bit Name History accumulation timer (expressed in milliseconds)
Description History accumulation timer, Bits[7:0] History accumulation timer, Bits[15:8] History accumulation timer, Bits[23:16]
Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).
Table 64. History Mode
Address 031B Bits [7:5] [4] Bit Name Unused Single-sample fallback Description Controls the holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then 0 (default) = use the free running frequency tuning word register value. 1 = use the last tuning word from the DPLL. Controls the holdover history initialization. When switching to a new reference 0 (default) = clear the tuning word history. 1 = retain the previous tuning word history. History mode value from 0 to 7 (default = 0).
[3]
Persistent history
[2:0]
Incremental average
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CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0400 TO REGISTER 0419)
Table 65. Distribution Settings 1
Address 0400 Bits [7:6] [5] Bit Name Unused External distribution resistor Receiver mode Description Output current control for the clock distribution outputs 0 (default) = internal current setting resistor 1 = external current setting resistor Clock distribution receiver mode 0 (default) = normal operation 1 = high frequency mode (super-Nyquist) Power-down clock distribution output OUT3 0 (default) = normal operation 1 = power-down Power-down clock distribution output OUT2 0 (default) = normal operation 1 = power-down Power-down clock distribution output OUT1 0 (default) = normal operation 1 = power-down Power-down clock distribution output OUT0 0 (default) = normal operation 1 = power-down
[4]
[3]
OUT3 power-down
[2]
OUT2 power-down
[1]
OUT1 power-down
[0]
OUT0 power-down
1
When Bits[3:0] = 1111, the clock distribution output enters a deep sleep mode.
Table 66. Distribution Enable
Address 0401 Bits [7:4] [3] Bit Name Unused OUT3 enable Description Enable the OUT3 driver. 0 (default) = disable. 1 = enable. Enable the OUT2 driver. 0 (default) = disable. 1 = enable. Enable the OUT1 driver. 0 (default) = disable. 1 = enable. Enable the OUT0 driver. 0 (default) = disable. 1 = enable.
[2]
OUT2 enable
[1]
OUT1 enable
[0]
OUT0 enable
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Table 67. Distribution Synchronization
Address 0402 Bits [7:6] [5:4] Bit Name Unused Sync source Description Select the sync source for the clock distribution output channels. 00 (default) = direct. 01 = active reference. 10 = DPLL feedback edge. 11 = reserved. Mask the synchronous reset to the OUT3 divider. 0 (default) = unmasked 1 = masked. Mask the synchronous reset to the OUT2 divider. 0 (default) = unmasked. 1 = masked. Mask the synchronous reset to the OUT1 divider. 0 (default) = unmasked. 1 = masked. Mask the synchronous reset to the OUT0 divider. 0 (default) = unmasked. 1 = masked.
[3]
OUT3 sync mask
[2]
OUT2 sync mask
[1]
OUT1 sync mask
[0]
OUT0 sync mask
Table 68. Automatic Synchronization
Address 0403 Bits [7:2] [1:0] Bit Name Unused Automatic sync mode Description Autosync mode 00 (default) = disabled 01 = sync on DPLL frequency lock 10 = sync on DPLL phase lock 11 = reserved
Table 69. Distribution Channel Modes
Address 0404 Bits [7:6] [5] Bit Name Unused OUT0 CMOS phase invert Description When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT0. 0 (default) = not inverted. 1 = inverted. OUT0 output drive capability control. 0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal. OUT0 operating mode select. 000 = CMOS (both pins) 001 = CMOS (positive pin), tristate (negative pin). 010 = tristate (positive pin), CMOS (negative pin). 011 (default) = tristate (both pins). 100 = LVDS. 101 = LVPECL. 110 = reserved. 111 = reserved.
[4]
OUT0 polarity invert
[3]
OUT0 drive strength
[2:0]
OUT0 mode
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Address 0405 Bits [7:6] [5] Bit Name Unused OUT1 CMOS phase invert Description When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT1. 0 (default) = not inverted. 1 = inverted. OUT1 output drive capability control. 0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal. OUT1 operating mode select. 000 = CMOS (both pins). 001 = CMOS (positive pin), tristate (negative pin). 010 = tristate (positive pin), CMOS (negative pin). 011 (default) = tristate (both pins). 100 = LVDS. 101 = LVPECL. 110 = reserved. 111 = reserved. When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT2. 0 (default) = not inverted. 1 = inverted. OUT2 output drive capability control. 0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal. OUT2 operating mode select. 000 = CMOS (both pins). 001 = CMOS (positive pin), tristate (negative pin). 010 = tristate (positive pin), CMOS (negative pin). 011 (default) = tristate (both pins). 100 = LVDS. 101 = LVPECL. 110 = reserved. 111 = reserved.
[4]
OUT1 polarity invert
[3]
OUT1 drive strength
[2:0]
OUT1 mode
0406
[7:6] [5]
Unused OUT2 CMOS phase invert
[4]
OUT2 polarity invert
[3]
OUT2 drive strength
[2:0]
OUT2 mode
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Address 0407 Bits [7:6] [5] Bit Name Unused OUT3 CMOS phase invert Description When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. Invert the polarity of OUT3. 0 (default) = not inverted. 1 = inverted. OUT3 output drive capability control. 0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal. OUT3 operating mode select. 000 = CMOS (both pins). 001 = CMOS (positive pin), tristate (negative pin). 010 = tristate (positive pin), CMOS (negative pin). 011 (default) = tristate (both pins). 100 = LVDS. 101 = LVPECL. 110 = reserved. 111 = reserved.
[4]
OUT3 polarity invert
[3]
OUT3 drive strength
[2:0]
OUT3 mode
Register 0408 to Register 0417--Distribution Channel Dividers
Table 70. Q0 Divider 1
Address 0408 0409 040A 040B Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q0 Description Q0 divider, Bits[7:0] Q0 divider, Bits[15:8] Q0 divider, Bits[23:16] Q0 divider, Bits[29:24]
Unused Q0
1
The default value is 0 (or divide by 1).
Table 71. Q1 Divider 1
Address 040C 040D 040E 040F Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q1 Description Q1 divider, Bits[7:0] Q1 divider, Bits[15:8] Q1 divider, Bits[23:16] Q1 divider, Bits[29:24]
Unused Q1
1
The default value is 0 (or divide by 1).
Table 72. Q2 Divider 1
Address 0410 0411 0412 0413 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q2 Description Q2 divider, Bits[7:0] Q2 divider, Bits[15:8] Q2 divider, Bits[23:16] Q2 divider, Bits[29:24]
Unused Q2
1
The default value is 0 (or divide by 1).
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Table 73. Q3 Divider 1
Address 0414 0415 0416 0417 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q3 Description Q3 divider, Bits[7:0] Q3 divider, Bits[15:8] Q3 divider, Bits[23:16] Q3 divider, Bits[29:24]
Unused Q3
1
The default value is 0 (or divide by 1).
REFERENCE INPUT CONFIGURATION (REGISTER 0500 TO REGISTER 0507)
Table 74. Reference Power-Down
When all bits are set, the reference receiver section enters a deep sleep mode.
Address 0500 Bits [7] Bit Name Ref DD power-down Description REF DD input receiver power-down 0 (default) = normal operation 1 = power-down REF D input receiver power-down 0 (default) = normal operation 1 = power-down REF CC input receiver power-down 0 (default) = normal operation 1 = power-down REF C input receiver power-down 0 (default) = normal operation 1 = power-down REF BB input receiver power-down 0 (default) = normal operation 1 = power-down REF B input receiver power-down 0 (default) = normal operation 1 = power-down REF AA input receiver power-down 0 (default) = normal operation 1 = power-down REF A input receiver power-down 0 (default) = normal operation 1 = power-down
[6]
Ref D power-down
[5]
Ref CC power-down
[4]
Ref C power-down
[3]
Ref BB power-down
[2]
Ref B power-down
[1]
Ref AA power-down
[0]
Ref A power-down
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Table 75. Reference Logic Family
Address 0501 Bits [7:6] Bit Name Ref BB logic family Description Select the logic family for the REF BB input receiver (ignored if Bits[5:4] = 00) 00 (default) = disabled 01 = 1.2 V to 1.5 V CMOS 10 = 1.8 V to 2.5 V CMOS 11 = 3.0 V to 3.3 V CMOS Select logic family for REF B input receiver. 00 (default) = differential (REFB/BB is positive/negative input) 01 = 1.2 V to 1.5 V CMOS 10 = 1.8 V to 2.5 V CMOS 11 = 3.0 V to 3.3 V CMOS The same as Register 0501, Bits[7:6] but for REF AA The same as Register 0501, Bits[5:4] but for REF A The same as Register 0501, Bits[7:6] but for REF DD The same as Register 0501, Bits[5:4] but for REF D The same as Register 0501, Bits[7:6] but for REF CC The same as Register 0501, Bits[5:4] but for REF C
[5:4]
Ref B logic family
0502
[3:2] [1:0] [7:6] [5:4] [3:2] [1:0]
Ref AA logic family Ref A logic family Ref DD logic family Ref D logic family Ref CC logic family Ref C logic family
Table 76. Manual Reference Profile Selection
Address 0503 Bits [7] Bit Name Enable Ref AA manual profile Ref AA manual profile Description Select manual or automatic reference profile assignment for REF AA 0 (default) = automatic 1 = manual Manual profile assignment 000 (default) = Profile 0 001 = Profile 1 010 = Profile 2 011 = Profile 3 100 = Profile 4 101 = Profile 5 110 = Profile 6 111 = Profile 7 Same as Register 0503, Bit 7 but for REF A Same as Register 0503, Bits[6:4] but for REF A Same as Register 0503, Bit 7 but for REF B Same as Register 0503, Bits[6:4] but for REF BB Same as Register 0503, Bit 7 but for REF B Same as Register 0503, Bits[6:4] but for REF B Same as Register 0503, Bit 7 but for REF CC Same as Register 0503, Bits[6:4] but for REF CC Same as Register 050, Bit 7 but for REF C Same as Register 0503, Bits[6:4] but for REF C Same as Register 0503, Bit 7 but for REF DD Same as Register 0503, Bits[6:4] but for REF DD Same as Register 0503, Bit 7 but for REF D Same as Register 0503, Bits[6:4] but for REF D
[6:4]
[3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0]
0504
0505
0506
Enable Ref A manual profile Ref A manual profile Enable Ref BB manual profile Ref BB manual profile Enable Ref B manual profile Ref B manual profile Enable Ref CC manual profile Ref CC manual profile Enable Ref C manual profile Ref C manual profile Enable Ref DD M manual profile Ref DD manual profile Enable Ref D manual profile Ref D manual profile
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Table 77. Phase Build-Out Switching
Address 0507 Bits [7:3] [2:0] Bit Name Unused Phase master threshold priority Description Threshold priority level (a value of 0 to 7, with 0 (default) being the highest priority level). References with a selection priority value lower than this value are treated as phase masters (see the Profile Registers (Register 0600 to Register 07FF) section for the selection priority value).
PROFILE REGISTERS (REGISTER 0600 TO REGISTER 07FF)
Note that the default value of every bit is 0 for Profile 0 to Profile 7.
Register 0600 to Register 0631--Profile 0
Table 78. Priorities--Profile 0
Address 0600 Bits [7:6] [5:3] Bit Name Unused Promoted priority Description User-assigned priority level (0 to 7) of the reference associated with Profile 0 while that reference is the active reference. The numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. User-assigned priority level (0 to 7) of the reference associated with Profile 0, which ranks that reference relative to the others.
[2:0]
Selection priority
Table 79. Reference Period--Profile 0
Address 0601 0602 0603 0604 0605 0606 0607 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2] [1:0] Bit Name Reference period (in femtoseconds) Description Nominal reference period, Bits[7:0] Nominal reference period, Bits[15:8] Nominal reference period, Bits[23:16] Nominal reference period, Bits[31:24] Nominal reference period, Bits[39:32] Nominal reference period, Bits[47:40] Nominal reference period, Bits[49:48]
Unused Reference period
Table 80. Tolerance--Profile 0
Address 0608 0609 060A 060B 060C 060D Bits [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0] Inner tolerance, Bits[15:8] Inner tolerance, Bits[19:16] Outer tolerance, Bits[7:0] Outer tolerance, Bits[5:8] Outer tolerance, Bits[19:16]
Table 81. Validation Timer--Profile 0
Address 060E 060F Bits [7:0] [7:0] Bit Name Validation timer (in milliseconds) Description Validation timer, Bits[7:0] Validation timer, Bits[15:8]
Table 82. Redetect Timer--Profile 0
Address 0610 0611 Bits [7:0] [7:0] Bit Name Redetect timer (in milliseconds) Description Redetect timer, Bits[7:0] Redetect timer, Bits[15:8]
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Table 83. Digital Loop Filter Coefficients--Profile 0 1
Address 0612 0613 0614 0615 0616 0617 Bits [7:0] [7:0] [7:6] [5:0] [7:1] [0] [7:0] [7] [6:2] [1:0] [7:0] [7:0] [7:6] [5:1] [0] [7:0] [7] [6:0] [7:4] [3:0] Bit Name Alpha-0 linear Alpha-2 exponent Alpha-1 exponent Beta-0 linear Alpha-2 exponent Beta-0 linear Unused Beta-1 exponent Beta-0 linear Gamma-0 linear Unused Gamma-1 exponent Gamma-0 linear Delta-0 linear Delta-1 exponent Delta-0 linear Alpha-3 exponent Delta-1 exponent Description Alpha-0 coefficient linear, Bits[7:0] Alpha-0 coefficient linear, Bits[15:8] Alpha-2 coefficient exponent, Bits[1:0] Alpha-1 coefficient exponent, Bits[5:0] Beta-0 coefficient linear, Bits[6:0] Alpha-2 coefficient exponent, Bit 2 Beta-0 coefficient linear, Bits[14:7] Beta-1 coefficient exponent, Bits[4:0] Beta-0 coefficient linear, Bits[16:15] Gamma-0 coefficient linear, Bits[7:0] Gamma -0 coefficient linear, Bits[15:8] Gamma-1 coefficient exponent, Bits[4:0] Gamma-0 coefficient linear, Bit 16 Delta-0 coefficient linear, Bits[7:0] Delta-1 coefficient exponent, Bit 0 Delta-0 coefficient linear, Bits[14:8] Alpha-3 coefficient exponent, Bits[3:0] Delta-1 coefficient exponent, Bits[4:1]
0618 0619 061A
061B 061C 061D
1
The digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.
Table 84. R-Divider--Profile 0 1
Address 061E 061F 0620 0621 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Description R, Bits[7:0] R, Bits[15:8] R, Bits[23:16] R, Bits[29:24]
Unused R
1
The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 85. S-Divider--Profile 0 1
Address 0622 0623 0624 0625 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name S Description S, Bits[7:0] S, Bits[15:8] S, Bits[23:16] S, Bits[29:24]
Unused S
1
The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
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Table 86. Fractional Feedback Divider--Profile 0
Address 0626 0627 Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4]
0628
Table 87. Lock Detectors--Profile 0
Address 0629 062A 062B 062C 062D 062E 062F 0630 0631 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold (in picoseconds) Phase lock fill rate Phase lock drain rate Frequency lock threshold (in picoseconds) Frequency lock fill rate Frequency lock drain rate Description Phase lock threshold, Bits[7:0] Phase lock threshold, Bits[15:8] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold, Bits[7:0] Frequency lock threshold, Bits[15:8] Frequency lock threshold, Bits[23:16] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0]
Register 0632 to Register 067F--Profile 1
Table 88. Priorities--Profile 1
Address 0632 Bits [7:6] [5:3] Bit Name unused Promoted priority Description User-assigned priority level (0 to 7) of the reference associated with Profile 1 while that reference is the active reference. The numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. User-assigned priority level (0 to 7) of the reference associated with Profile 1, which ranks that reference relative to the others.
[2:0]
Selection priority
Table 89. Reference Period--Profile 1
Address 0633 0634 0635 0636 0637 0638 0639 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2] [1:0] Bit Name Reference period (in femtoseconds) Description Nominal reference period, Bits[7:0] Nominal reference period, Bits[15:8] Nominal reference period, Bits[23:16] Nominal reference period, Bits[31:24] Nominal reference period, Bits[39:32] Nominal reference period, Bits[47:40] Nominal reference period, Bits[49:48]
Unused Reference period
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Table 90. Tolerance--Profile 1
Address 063A 063B 063C 063D 063E 063F Bits [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0] Inner tolerance, Bits[15:8] Inner tolerance, Bits[19:16] Outer tolerance, Bits[7:0] Outer tolerance, Bits[15:8] Outer tolerance, Bits[19:16]
Table 91. Validation Timer--Profile 1
Address 0640 0641 Bits [7:0] [7:0] Bit Name Validation timer (in milliseconds) Description Validation timer, Bits[7:0] Validation timer, Bits[15:8]
Table 92. Redetect Timer--Profile 1
Address 0642 0643 Bits [7:0] [7:0] Bit Name Redetect timer (in milliseconds) Description Redetect timer, Bits[7:0] Redetect timer, Bits[15:8]
Table 93. Digital Loop Filter Coefficients--Profile 1 1
Address 0644 0645 0646 0647 0648 0649 Bits [7:0] [7:0] [7:6] [5:0] [7:1] [0] [7:0] [7] [6:2] [1:0] [7:0] [7:0] [7:6] [5:1] [0] [7:0] [7] [6:0] [7:4] [3:0] Bit Name Alpha-0 linear Alpha-2 exponent Alpha-1 exponent Beta -0 linear Alpha-2 exponent Beta-0 linear Unused Beta-1 exponent Beta-0 linear Gamma-0 linear Unused Gamma-1 exponent Gamma-0 linear Delta-0 linear Delta-1 exponent Delta-0 linear Alpha-3 exponent Delta-1 exponent Description Alpha-0 coefficient linear, Bits[7:0] Alpha-0 coefficient linear, Bits[15:8] Alpha-2 coefficient exponent, Bits[1:0] Alpha-1 coefficient exponent, Bits[5:0] Beta-0 coefficient linear, Bits[6:0] Alpha-2 coefficient exponent, Bit 2 Beta-0 coefficient linear, Bits[14:7] Beta-1 coefficient exponent, Bits[4:0] Beta-0 coefficient linear, Bits[16:15] Gamma-0 coefficient linear, Bits[7:0] Gamma-0 coefficient linear, Bits[15:8] Gamma-1 coefficient exponent, Bits[4:0] Gamma-0 coefficient linear, Bit 16 Delta-0 coefficient linear, Bits[7:0] Delta-1 coefficient exponent, Bit 0 Delta-0 coefficient linear, Bits[14:8] Alpha-3 coefficient exponent, Bits[3:0] Delta-1 coefficient exponent, Bits[4:1]
064A 064B 064C
064D 064E 064F
1
The digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.
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Table 94. R-Divider--Profile 1 1
Address 0650 0651 0652 0653 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Description R, Bits[7:0] R, Bits[15:8] R, Bits[23:16] R, Bits[29:24]
Unused R
1
The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 95. S-Divider--Profile 1 1
Address 0654 0655 0656 0657
1
Bits [7:0] [7:0] [7:0] [7:6] [5:0]
Bit Name S
Description S, Bits[7:0] S, Bits[15:8] S, Bits[23:16] S, Bits[29:24]
Unused S
The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 96. Fractional Feedback Divider--Profile 1
Address 0658 0659 Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4]
065A
Table 97. Lock Detectors--Profile 1
Address 065B 065C 065D 065E 065F 0660 0661 0662 0663 0664 to 067F Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold (in picoseconds) Phase lock fill rate Phase lock drain rate Frequency lock threshold (in picoseconds) Frequency lock fill rate Frequency lock drain rate Unused Description Phase lock threshold, Bits[7:0] Phase lock threshold, Bits[15:8] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold, Bits[7:0] Frequency lock threshold, Bits[15:8] Frequency lock threshold, Bits[23:16] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0]
Register 0680 to Register 06B1--Profile 2
Table 98. Priorities--Profile 2
Address 0680 Bits [7:6] [5:3] Bit Name Unused Promoted priority Description User-assigned priority level (0 to 7) of the reference associated with Profile 2 while that reference is the active reference. The numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. User-assigned priority level (0 to 7) of the reference associated with Profile 2, which ranks that reference relative to the others.
[2:0]
Selection priority
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Table 99. Reference Period--Profile 2
Address 0681 0682 0683 0684 0685 0686 0687 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2] [1:0] Bit Name Reference period (in femtoseconds) Description Nominal reference period, Bits[7:0] Nominal reference period, Bits[15:8] Nominal reference period, Bits[23:16] Nominal reference period, Bits[31:24] Nominal reference period, Bits[39:32] Nominal reference period, Bits[47:40] Nominal reference period, Bits[49:48]
Unused Reference period
Table 100. Tolerance--Profile 2
Address 0688 0689 068A 068B 068C 068D Bits [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0] Inner tolerance, Bits[15:8] Inner tolerance, Bits[19:16] Outer tolerance, Bits[7:0] Outer tolerance, Bits[15:8] Outer tolerance, Bits[19:16]
Table 101. Validation Timer--Profile 2
Address 068E 068F Bits [7:0] [7:0] Bit Name Validation timer (in milliseconds) Description Validation timer, Bits[7:0] Validation timer, Bits[15:8]
Table 102. Redetect Timer--Profile 2
Address 0690 0691 Bits [7:0] [7:0] Bit Name Redetect timer (in milliseconds) Description Redetect timer, Bits[7:0] Redetect timer, Bits[15:8]
Table 103. Digital Loop Filter Coefficients--Profile 2 1
Address 0692 0693 0694 0695 0696 0697 Bits [7:0] [7:0] [7:6] [5:0] [7:1] [0] [7:0] [7] [6:2] [1:0] [7:0] [7:0] [7:6] [5:1] [0] [7:0] Bit Name Alpha-0 linear Alpha-2 exponent Alpha-1 exponent Beta-0 linear Alpha-2 exponent Beta 0-linear Unused Beta-1 exponent Beta-0 linear Gamma-0 linear Unused Gamma-1 exponent Gamma-0 linear Delta -0 linear Description Alpha-0 coefficient linear, Bits[7:0] Alpha-0 coefficient linear, Bits[15:8] Alpha-2 coefficient exponent, Bits[1:0] Alpha-1 coefficient exponent, Bits[5:0] Beta-0 coefficient linear, Bits[6:0] Alpha-2 coefficient exponent, Bit 2 Beta-0 coefficient linear, Bits[14:7] Beta-1 coefficient exponent, Bits[4:0] Beta-0 coefficient linear, Bits[16:15] Gamma-0 coefficient linear, Bits[7:0] Gamma-0 coefficient linear, Bits[15:8] Gamma-1 coefficient exponent, Bits[4:0] Gamma-0 coefficient linear, Bit 6 Delta-0 coefficient linear, Bits[7:0]
0698 0699 069A
069B
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Address 069C 069D Bits [7] [6:0] [7:4] [3:0] Bit Name Delta-1 exponent Delta-0 linear Alpha-3 exponent Delta-1 exponent Description Delta-1 coefficient exponent, Bit 0 Delta-0 coefficient linear, Bits[14:8] Alpha-3 coefficient exponent, Bits[3:0] Delta-1 coefficient exponent, Bits[4:1]
1
The digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.
Table 104. R-Divider--Profile 2 1
Address 069E 069F 06A0 06A1 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Description R, Bits[7:0] R, Bits[15:8] R, Bits[23:16] R, Bits[29:24]
Unused R
1
The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 105. S-Divider--Profile 2 1
Address 06A2 06A3 06A4 06A5 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name S Description S, Bits[7:0] S, Bits[15:8] S, Bits[23:16] S, Bits[29:24]
Unused S
1
The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 106. Fractional Feedback Divider--Profile 2
Address 06A6 06A7 Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4]
06A8
Table 107. Lock Detectors--Profile 2
Address 06A9 06AA 06AB 06AC 06AD 06AE 06AF 06B0 06B1 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold (in picoseconds) Phase lock fill rate Phase lock drain rate Frequency lock threshold (in picoseconds) Frequency lock fill rate Frequency lock drain rate Description Phase lock threshold, Bits[7:0] Phase lock threshold, Bits[15:8] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold, Bits[7:0] Frequency lock threshold, Bits[15:8] Frequency lock threshold, Bits[23:16] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0]
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Register 06B2 to Register 07FF--Profile 3
Table 108. Priorities--Profile 3
Address 06B2 Bits [7:6] [5:3] Bit Name Unused Promoted priority Description User-assigned priority level (0 to 7) of the reference associated with Profile 3 while that reference is the active reference. The numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. User-assigned priority level (0 to 7) of the reference associated with Profile 3, which ranks that reference relative to the others.
[2:0]
Selection priority
Table 109. Reference Period--Profile 3
Address 06B3 06B4 06B5 06B6 06B7 06B8 06B9 Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2] [1:0] Bit Name Reference period (in femtoseconds) Description Nominal reference period, Bits[7:0] Nominal reference period, Bits[15:8] Nominal reference period, Bits[23:16] Nominal reference period, Bits[31:24] Nominal reference period, Bits[39:32] Nominal reference period, Bits[47:40] Nominal reference period, Bits[49:48]
Unused Reference period
Table 110. Tolerance--Profile 3
Address 06BA 06BB 06BC 06BD 06BE 06BF Bits [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0] Inner tolerance, Bits[15:8] Inner tolerance, Bits[19:16] Outer tolerance, Bits[7:0] Outer tolerance, Bits[15:8] Outer tolerance, Bits[19:16]
Table 111. Validation Timer--Profile 3
Address 06C0 06C1 Bits [7:0] [7:0] Bit Name Validation timer (in milliseconds) Description Validation timer, Bits[7:0] Validation timer, Bits[15:8]
Table 112. Redetect Timer--Profile 3
Address 06C2 06C3 Bits [7:0] [7:0] Bit Name Redetect timer (in milliseconds) Description Redetect timer, Bits[7:0] Redetect timer, Bits[15:8]
Table 113. Digital Loop Filter Coefficients--Profile 3 1
Address 06C4 06C5 06C6 06C7 06C8 06C9 Bits [7:0] [7:0] [7:6] [5:0] [7:1] [0] [7:0] [7] [6:2] [1:0] Bit Name Alpha-0 linear Alpha-2 exponent Alpha-1 exponent Beta-0 linear Alpha-2 exponent Beta-0 linear Unused Beta-1 exponent Beta-0 linear Description Alpha-0 coefficient linear, Bits[7:0] Alpha-0 coefficient linear, Bits[15:8] Alpha-2 coefficient exponent, Bits[1:0] Alpha-1 coefficient exponent, Bits[5:0] Beta-0 coefficient linear, Bits[6:0] Alpha-2 coefficient exponent, Bit 2 Beta-0 coefficient linear, Bits[14:7] Beta-1 coefficient exponent, Bits[4:0] Beta-0 coefficient linear, Bits[16:15]
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Address 06CA 06CB 06CC Bits [7:0] [7:0] [7:6] [5:1] [0] [7:0] [7] [6:0] [7:4] [3:0] Bit Name Gamma-0 linear Unused Gamma-1 exponent Gamma-0 linear Delta-0 linear Delta-1 exponent Delta-0 linear Alpha-3 exponent Delta-1 exponent Description Gamma-0 coefficient linear, Bits[7:0] Gamma-0 coefficient linear, Bits[15:8] Gamma-1 coefficient exponent, Bits[4:0] Gamma-0 coefficient linear, Bit 16 Delta-0 coefficient linear, Bits[7:0] Delta-1 coefficient exponent, Bit 0 Delta-0 coefficient linear, Bits[14:8] Alpha-3 coefficient exponent, Bits[3:0] Delta-1 coefficient exponent, Bits[4:1]
06CD 06CE 06CF
1
The digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.
Table 114. R Divider--Profile 3 1
Address 06D0 06D1 06D2 06D3 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Description R, Bits[7:0] R, Bits[15:8] R, Bits[23:16] R, Bits[29:24]
Unused R
1
The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.
Table 115. S Divider--Profile 3 1
Address 06D4 06D5 06D6 06D7 Bits [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name S Description S, Bits[7:0] S, Bits[15:8] S, Bits[23:16] S, Bits[29:24]
Unused S
1
The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 116. Fractional Feedback Divider--Profile 3
Address 06D8 06D9 Bits [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0] U, Bits[3:0] V, Bits[9:8] U, Bits[9:4]
06DA
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Table 117. Lock Detectors--Profile 3
Address 06DB 06DC 06DD 06DE 06DF 06E0 06E1 06E2 06E3 06E4 to 06FF Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold (in picoseconds) Phase lock fill rate Phase lock drain rate Frequency lock threshold (in picoseconds) Frequency lock fill rate Frequency lock drain rate Unused Description Phase lock threshold, Bits[7:0] Phase lock threshold, Bits[15:8] Phase lock fill rate, Bits[7:0] Phase lock drain rate, Bits[7:0] Frequency lock threshold, Bits[7:0] Frequency lock threshold, Bits[15:8] Frequency lock threshold, Bits[23:16] Frequency lock fill rate, Bits[7:0] Frequency lock drain rate, Bits[7:0]
Register 0700 to Register 07FF--Profile 4 to Profile 7
Profile 4 (Register 0700 to Register 0731) is identical to Profile 0 (Register 0600 to Register0631). Profile 5 (Register 0732 to Register 077F) is identical to Profile 1 (Register 0632 to Register 067F). Profile 6 (Register 0780 to Register 07B1) is identical to Profile 2 (Register 0680 to Register 06B1). Profile 7 (Register 07B2 to Register 07FF) is identical to Profile 3 (Register 06B2 to Register 06FF).
OPERATIONAL CONTROLS (REGISTER 0A00 TO REGISTER 0A10)
Table 118. General Power-Down
Address 0A00 Bits [7] Bit Name Reset sans reg map Description Reset internal hardware but retain programmed register values. 0 (default) = normal operation. 1 = reset. Place SYSCLK input and PLL in deep sleep mode. 0 (default) = normal operation. 1 = power-down. Place reference clock inputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. Place the time-to-digital converter in deep sleep mode. 0 (default) = normal operation. 1 = power-down. Place the DAC in deep sleep mode. 0 (default) = normal operation. 1 = power-down. Place the clock distribution outputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. Place the entire device in deep sleep mode. 0 (default) = normal operation. 1 = power-down.
[6] [5]
Unused SYSCLK power-down
[4]
Reference powerdown TDC power-down
[3]
[2]
DAC power-down
[1]
Dist power-down
[0]
Full power-down
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Table 119. Loop Mode
Address 0A01 Bits [7] [6] Bit Name Unused User holdover Description Force the device into holdover mode. 0 (default) = normal operation. 1 = force device into holdover mode. The device behaves as though all input references are faulted. Force the device into free-run mode. 0 (default) = normal operation. 1 = force device into free-run mode. The free running frequency tuning word register specifies the DDS output frequency. Note that, when the user freerun bit is set, it overrides the user holdover bit. Select the operating mode of the reference switching state machine. 00 (default) = automatic mode. The fully automatic priority-based algorithm selects the active reference (Bits[2:0] are ignored). 01 = fallback mode. The active reference is the user reference (Bits[2:0]) as long as it is valid. Otherwise, use the fully automatic priority-based algorithm to select the active reference. 10 = holdover mode. The active reference is the user reference (Bits[2:0]) as long as it is valid. Otherwise, enter holdover mode. 11 = manual mode. The active reference is always the user reference (Bits[2:0]). When using manual mode, be sure that the reference declared as the user reference (Bits[2:0]) is programmed for manual reference-to-profile assignment in the appropriate manual reference profile selection register (Address 0503 to Address 0506). Input reference when user selection mode = 01, 10, or 11. 000 (default) = Input Reference A 001 = Input Reference AA 010 = Input Reference B 011 = Input Reference BB 100 = Input Reference C 101 = Input Reference CC 110 = Input Reference D 111 = Input Reference DD
[5]
User freerun
[4:3]
User selection mode
[2:0]
User reference selection
Table 120. Cal/Sync
Address 0A02 Bits [7:2] [1] Bit Name unused Sync distribution Description Setting this bit (default = 0) initiates synchronization of the clock distribution output. While this bit = 1, the clock distribution output stalls. Synchronization occurs on the 1 to 0 transition of this bit. Setting this bit (default = 0) initiates an internal calibration of the SYSCLK PLL (assuming it is enabled). The calibration routine automatically selects the proper VCO frequency band and signal amplitude. The internal system clock stalls during the calibration procedure, disabling the device until the calibration is complete (a few milliseconds).
[0]
Calibrate system clock
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Register 0A03--ResetFunc
Table 121. Reset Functions 1
Address 0A03 Bits [7] [6] [5] [4] [3] [2] [1] Bit Name Unused Clear LF Clear CCI Clear phase accumulator Reset auto sync Reset TW history Reset all IRQs Description Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). Setting this bit (default = 0) clears the CCI filter (intended as a debug tool). Setting this bit (default = 0) clears DDS phase accumulator (not a recommended action). Setting this bit (default = 0) resets the automatic synchronization logic (see Register 0403). Setting this bit (default = 0) resets the tuning word history logic (part of holdover functionality). Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0D02 to Register 0D09). It is the equivalent of setting all the bits of the IRQ clearing register (Register 0A04 to Register 0A0B). Setting this bit (default = 0) resets the watchdog timer (see Register 0211 to Register 0212). If the timer had timed out, it simply starts a new timing cycle. If the timer has not yet timed out, it restarts at time zero without causing a timeout event. Continuously resetting the watchdog timer at intervals less than its timeout period prevents the watchdog timer from generating a timeout event.
[0]
Reset watchdog
1
All bits in this register are autoclearing.
Register 0A04 to Register 0A0B--IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0D02 to Address 0D09). When set to Logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing register is an autoclearing register.
Table 122. IRQ Clearing for SYSCLK
Address 0A04 Bits [7:6] [5] [4] [3:2] [1] [0] Bit Name Unused SYSCLK unlocked SYSCLK locked Unused SYSCLK Cal complete SYSCLK Cal started Description Clears SYSCLK unlocked IRQ Clears SYSCLK locked IRQ Clears SYSCLK calibration complete IRQ Clears SYSCLK calibration started IRQ
Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address 0A05 Bits [7:4] [3] [2] [1] [0] Bit Name Unused Distribution sync Watchdog timer EEPROM fault EEPROM complete Description Clears distribution sync IRQ Clears watchdog timer IRQ Clears EEPROM fault IRQ Clears EEPROM complete IRQ
Table 124. IRQ Clearing for the Digital PLL
Address 0A06 Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Switching Closed Freerun Holdover Freq unlocked Freq locked Phase unlocked Phase locked Description Clears switching IRQ Clears closed IRQ Clears freerun IRQ Clears holdover IRQ Clears frequency unlocked IRQ Clears frequency locked IRQ Clears phase unlocked IRQ Clears phase locked IRQ
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Table 125. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit
Address 0A07 Bits [7:5] [4] [3] [2] [1] [0] Bit Name Unused History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Clears history updated IRQ Clears frequency unclamped IRQ Clears frequency clamped IRQ Clears phase slew unlimited IRQ Clears phase slew limited IRQ
Table 126. IRQ Clearing for Reference Inputs
Address 0A08 Bits [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Ref AA new profile Ref AA validated Ref AA fault cleared Ref AA fault Ref A new profile Ref A validated Ref A fault cleared Ref A fault Ref BB new profile Ref BB validated Ref BB fault cleared Ref BB fault Ref B new profile Ref B validated Ref B fault cleared Ref B fault Ref CC new profile Ref CC validated Ref CC fault cleared Ref CC fault Ref C new profile Ref C validated Ref C fault cleared Ref C fault Ref DD new profile Ref DD validated Ref DD fault cleared Ref DD fault Ref D new profile Ref D validated Ref D fault cleared Ref D fault Description Clears Ref AA new profile IRQ Clears Ref AA validated IRQ Clears Ref AA fault cleared IRQ Clears Ref AA fault IRQ Clears Ref A new profile IRQ Clears Ref A validated IRQ Clears Ref A fault cleared IRQ Clears Ref A fault IRQ Clears Ref BB new profile IRQ Clears Ref BB validated IRQ Clears Ref BB fault cleared IRQ Clears Ref BB fault IRQ Clears Ref B new profile IRQ Clears Ref B validated IRQ Clears Ref B fault cleared IRQ Clears Ref B fault IRQ Clears Ref CC new profile IRQ Clears Ref CC validated IRQ Clears Ref CC fault cleared IRQ Clears Ref CC fault IRQ Clears Ref C new profile IRQ Clears Ref C validated IRQ Clears Ref C fault cleared IRQ Clears Ref C fault IRQ Clears Ref DD new profile IRQ Clears Ref DD validated IRQ Clears Ref DD fault cleared IRQ Clears Ref DD fault IRQ Clears Ref D new profile IRQ Clears Ref D validated IRQ Clears Ref D fault cleared IRQ Clears Ref D fault IRQ
0A09
0A0A
0A0B
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Table 127. Incremental Phase Offset Control
Address 0A0C Bits [7:3] [2] [1] Bit Name Unused Reset phase offset Decr phase offset Description Resets the incremental phase offset to 0. This is an autoclearing bit. Decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size register (Register 0314 to Register 0315). This is an autoclearing bit. Increments the incremental phase offset by the amount specified in the incremental phase lock offset step size register (Register 0314 to Register 0315). This is an autoclearing bit.
[0]
Incr phase offset
Table 128. Reference Profile Selection State Machine Startup 1
Address 0A0D Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Detect DD Detect D Detect CC Detect C Detect BB Detect B Detect AA Detect A Description Setting this bit starts the profile selection state machine for Input Reference DD. Setting this bit starts the profile selection state machine for Input Reference D. Setting this bit starts the profile selection state machine for Input Reference CC. Setting this bit starts the profile selection state machine for Input Reference C. Setting this bit starts the profile selection state machine for Input Reference BB. Setting this bit starts the profile selection state machine for Input Reference B. Setting this bit starts the profile selection state machine for Input Reference AA. Setting this bit starts the profile selection state machine for Input Reference A.
1
All bits in this register are autoclearing.
Table 129. Reference Validation Override Controls 1
Address 0A0E Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Force Timeout DD Force Timeout D Force Timeout CC Force Timeout C Force Timeout BB Force Timeout B Force Timeout AA Force Timeout A Description Setting this bit emulates a timeout of the validation timer for Reference DD. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference D. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference CC. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference C. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference BB. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference B. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference AA. This is an autoclearing bit. Setting this bit emulates a timeout of the validation timer for Reference A. This is an autoclearing bit.
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Address 0A0F Bits [7] [6] [5] [4] [3] [2] [1] [0] 0A10 [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Ref Mon Override DD Ref Mon Override D Ref Mon Override CC Ref Mon Override C Ref Mon Override BB Ref Mon Override B Ref Mon Override AA Ref Mon Override A Ref Mon Bypass DD Ref Mon Bypass D Ref Mon Bypass CC Ref Mon Bypass C Ref Mon Bypass BB Ref Mon Bypass B Ref Mon Bypass AA Ref Mon Bypass A Description Overrides the reference monitor REF fault signal for Reference DD (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference D (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference CC (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference C (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference BB (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference B (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference AA (default = 0, not overridden). Overrides the reference monitor REF fault signal for Reference A (default = 0, not overridden). Bypasses the reference monitor for Reference DD (default = 0, not bypassed). Bypasses the reference monitor for Reference D (default = 0, not bypassed). Bypasses the reference monitor for Reference CC (default = 0, not bypassed). Bypasses the reference monitor for Reference C (default = 0, not bypassed). Bypasses the reference monitor for Reference BB (default = 0, not bypassed). Bypasses the reference monitor for Reference B (default = 0, not bypassed). Bypasses the reference monitor for Reference AA (default = 0, not bypassed). Bypasses the reference monitor for Reference A (default = 0, not bypassed).
1
See Figure 34 for details.
STATUS READBACK (REGISTER 0D00 TO REGISTER 0D19)
All bits in Register 0D00 to Register 0D19 are read only.
Table 130. EEPROM Status
Address 0D00 Bits [7:3] [2] [1] [0] Bit Name Unused Fault detected Load in progress Save in progress Description An error occurred while saving data to or loading data from the EEPROM. The control logic sets this bit while data is being read from the EEPROM. The control logic sets this bit while data is being written to the EEPROM.
Table 131. SYSCLK Status
Address 0D01 Bits [7:5] [4] [3:2] [1] [0] Bit Name Unused Stable Unused Cal in progress Lock detected Description The control logic sets this bit when the device considers the system clock to be stable (see the System Clock Stability Timer section). The control logic holds this bit set while the system clock calibration is in progress. Indicates the status of the system clock PLL. 0 = unlocked. 1 = locked (or the PLL is disabled).
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AD9548
Register 0D02 to Register 0D09--IRQ Monitor
If not masked via the IRQ mask register (Address 0209 to Address 0210), then the appropriate IRQ monitor bit is set to a Logic 1 when the indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0A04 to Address 0A0B), the reset all IRQs bit (Register 0A03, Bit 1), or a device reset.
Table 132. IRQ Monitor for SYSCLK
Address 0D02 Bits [7:6] [5] [4] [3:2] [1] [0] Bit Name Unused SYSCLK unlocked SYSCLK locked Unused SYSCLK Cal complete SYSCLK Cal started Description Indicates a SYSCLK PLL state transition from locked to unlocked Indicates a SYSCLK PLL state transition from unlocked to locked Indicates that SYSCLK calibration has completed Indicates that SYSCLK calibration has begun
Table 133. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address 0D03 Bits [7:4] [3] [2] [1] [0] Bit Name Unused Distribution sync Watchdog timer EEPROM fault EEPROM complete Description Indicates a distribution sync event Indicates expiration of the watchdog timer Indicates a fault during an EEPROM load or save operation Indicates successful completion of an EEPROM load or save operation
Table 134. IRQ Monitor for the Digital PLL
Address 0D04 Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Switching Closed Freerun Holdover Freq unlocked Freq locked Phase unlocked Phase locked Description Indicates that the DPLL is switching to a new reference Indicates that the DPLL has entered closed-loop operation Indicates that the DPLL has entered free-run mode Indicates that the DPLL has entered holdover mode Indicates that the DPLL lost frequency lock Indicates that the DPLL has acquired frequency lock Indicates that the DPLL lost phase lock Indicates that the DPLL has acquired phase lock
Table 135. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address 0D05 Bits [7:5] [4] [3] [2] [1] [0] Bit Name Unused History updated Freq unclamped Freq clamped Phase slew unlimited Phase slew limited Description Indicates the occurrence of a tuning word history update Indicates a frequency limiter state transition from clamped to unclamped Indicates a frequency limiter state transition from unclamped to clamped Indicates a phase slew limiter state transition from slew limiting to not slew limiting Indicates a phase slew limiter state transition from not slew limiting to slew limiting
Table 136. IRQ Monitor for Reference Inputs
Address 0D06 Bits [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Ref AA new profile Ref AA validated Ref AA fault cleared Ref AA fault Ref A new profile Ref A validated Ref A fault cleared Ref A fault Description Indicates that Ref AA has switched to a new profile Indicates that Ref AA has been validated Indicates that Ref AA has been cleared of a previous fault Indicates that Ref AA has been faulted Indicates that Ref A has switched to a new profile Indicates that Ref A has been validated Indicates that Ref A has been cleared of a previous fault Indicates that Ref A has been faulted
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Address 0D07 Bits [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] Bit Name Ref BB new profile Ref BB validated Ref BB fault cleared Ref BB fault Ref B new profile Ref B validated Ref B fault cleared Ref B fault Ref CC new profile Ref CC validated Ref CC fault cleared Ref CC fault Ref C new profile Ref C validated Ref C fault cleared Ref C fault Ref DD new profile Ref DD validated Ref DD fault cleared Ref DD fault Ref D new profile Ref D validated Ref D fault cleared Ref D fault Description Indicates that Ref BB has switched to a new profile Indicates that Ref BB has been validated Indicates that Ref BB has been cleared of a previous fault Indicates that Ref BB has been faulted Indicates that Ref B has switched to a new profile Indicates that Ref B has been validated Indicates that Ref B has been cleared of a previous fault Indicates that Ref B has been faulted Indicates that Ref CC has switched to a new profile Indicates that Ref CC has been validated Indicates that Ref CC has been cleared of a previous fault Indicates that Ref CC has been faulted Indicates that Ref C has switched to a new profile Indicates that Ref C has been validated Indicates that Ref C has been cleared of a previous fault Indicates that Ref C has been faulted Indicates that Ref DD has switched to a new profile Indicates that Ref DD has been validated Indicates that Ref DD has been cleared of a previous fault Indicates that Ref DD has been faulted Indicates that Ref D has switched to a new profile Indicates that Ref D has been validated Indicates that Ref D has been cleared of a previous fault Indicates that Ref D has been faulted
0D08
0D09
Table 137. DPLL Status
Address 0D0A Bits [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5:3] Bit Name Offset slew limiting Phase build-out Freq lock Phase lock Loop switching Holdover Active Free running Frequency clamped History available Active reference priority Active reference Description The current closed-loop phase offset is rate limited. A phase build-out transition was made to the currently active reference. The DPLL has achieved frequency lock. The DPLL has achieved phase lock. The DPLL is in the process of a reference switchover. The DPLL is in holdover mode. The DPLL is active (that is, operating in a closed-loop condition) The DPLL is free running (that is, operating in an open-loop condition) The upper or lower frequency tuning word clamp is in effect. There is sufficient tuning word history available for holdover operation. Priority value of the currently active reference. 000 = highest priority. 111 = lowest priority. Index of the currently active reference. 000 = Reference A. 001 = Reference AA. 010 = Reference B. 011 = Reference BB. 100 = Reference C. 101 = Reference CC. 110 = Reference D. 111 = Reference DD.
0D0B
[2:0]
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Table 138. Input Reference Status
Address 0D0C Bits [7] [6:4] [3] [2] [1] Bit Name Profile selected Selected profile Valid Fault Fast Description The control logic sets this bit when it assigns Ref A to one of the eight profiles. The index (0 to 7) of the profile assigned to Ref A. Note that these bits are meaningless unless Bit 7 = 1. Ref A is valid for use (it is unfaulted and its validation timer has expired). Ref A is not valid for use. If Bit 7 = 1, then this bit indicates that the frequency of Ref A is higher than allowed by its profile settings. If Bit 7 = 0, then this bit indicates that the frequency of Ref A is above the maximum input reference frequency supported by the device. If Bit 7 = 1, then this bit indicates that the frequency of Ref A is lower than allowed by its profile settings. If Bit 7 = 0, then this bit indicates that the frequency of Ref A is below the minimum input reference frequency supported by the device. Same as 0D0C but for REF AA instead of REF A. Same as 0D0C but for REF B instead of REF A. Same as 0D0C but for REF BB instead of REF A. Same as 0D0C but for REF C instead of REF A. Same as 0D0C but for REF CC instead of REF A. Same as 0D0C but for REF D instead of REF A. Same as 0D0C but for REF DD instead of REF A.
[0]
Slow
0D0D 0D0E 0D0F 0D10 0D11 0D12 0D13
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Table 139. Holdover History 1
Address 0D14 0D15 0D16 0D17 0D18 0D19
1
Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Bit Name Holdover history
Description Tuning word readback, Bits[7:0] Tuning word readback, Bits[15:8] Tuning word readack, Bits[23:9] Tuning word readback, Bits[31:24] Tuning word readback, Bits[39:32] Tuning word readback, Bits[47:40]
These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic.
NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0E00 TO REGISTER 0E03)
Table 140. EEPROM Control
Address 0E00 Bits [7:2] [1] Bit Name Unused Half rate mode Description EEPROM serial communication rate. 0 (default) = 400 kHz (normal). 1 = 200 kHz. EEPROM write enable/protect. 0 (default) = EEPROM write protected. 1 = EEPROM write enabled. When set to a nonzero value (default = 0), these bits establish the condition for EEPROM downloads. Upload data to the EEPROM based on the EEPROM storage sequence. This is an autoclearing bit. Download data from the EEPROM. This is an autoclearing bit.
[0]
Write enable
0E01
[7:5] [4:0] [7:1] 0 [7:2] [1] [0]
Unused Condition value Unused Save to EEPROM Unused Load from EEPROM Unused
0E02
0E03
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EEPROM STORAGE SEQUENCE (REGISTER 0E10 TO REGISTER 0E3F)
The default settings of Register 0E10 to Register 0E33 embody a sample scratch pad instruction sequence. The following is a description of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage sequence.
Table 141. EEPROM Storage Sequence for System Clock Settings
Address 0E10 Bits [7:0] Bit Name System clock Description The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0100. Note that Register 0E11 and Register 0E12 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to the system clock parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
0E11 0E12
[7:0] [7:0]
System clock
0E13
[7:0]
I/O update
Table 142. EEPROM Storage Sequence for System Clock Calibration
Address 0E14 Bits [7:0] Bit Name SYSCLK calibrate Description The default value of this register is 0xA0, which the controller interprets as a calibrate instruction. The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.
Table 143. EEPROM Storage Sequence for General Configuration Settings
Address 0E15 Bits [7:0] Bit Name General Description The default value of this register is 0x14, which the controller interprets as a data instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the address specified by the next two bytes. The controller stores 0x14 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0200. Note that Register 0E16 and Register 0E17 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 21 bytes from the register map (beginning at Address 0x0200) to the EEPROM and increments the EEPROM address pointer by 22 (21 data bytes and one checksum byte). The 21 bytes transferred correspond to the general configuration parameters in the register map.
0E16 0E17
[7:0] [7:0]
General
Table 144. EEPROM Storage Sequence for DPLL Settings
Address 0E18 Bits [7:0] Bit Name DPLL Description The default value of this register is 0x1B, which the controller interprets as a data instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the address specified by the next two bytes. The controller stores 0x1B in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0300. Note that Register 0E19 and Register 0E1A are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 28 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments the EEPROM address pointer by 29 (28 data bytes and one checksum byte). The 28 bytes transferred correspond to the DPLL parameters in the register map.
0E19 0E1A
[7:0] [7:0]
DPLL
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Table 145. EEPROM Storage Sequence for Clock Distribution Settings
Address 0E1B Bits [7:0] Bit Name Clock distribution Description The default value of this register is 0x19, which the controller interprets as a data instruction. Its decimal value is 25, which tells the controller to transfer 26 bytes of data (25 + 1) beginning at the address specified by the next two bytes. The controller stores 0x19 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0400. Note that Register 0E1C and Register 0E1D are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0400). The controller stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 26 bytes from the register map (beginning at Address 0x0400) to the EEPROM and increments the EEPROM address pointer by 27 (26 data bytes and one checksum byte). The 26 bytes transferred correspond to the clock distribution parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
0E1C 0E1D
[7:0] [7:0]
Clock distribution
0E1E
[7:0]
I/O update
Table 146. EEPROM Storage Sequence for Reference Input Settings
Address 0E1F Bits [7:0] Bit Name Reference inputs Description The default value of this register is 0x07, which the controller interprets as a data instruction. Its decimal value is 7, which tells the controller to transfer eight bytes of data (7 + 1) beginning at the address specified by the next two bytes. The controller stores 0x07 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0500. Note that Register 0E20 and Register 0E21 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0500). The controller stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then transfers eight bytes from the register map (beginning at Address 0x0500) to the EEPROM and increments the EEPROM address pointer by nine (eight data bytes and one checksum byte). The eight bytes transferred correspond to the reference inputs parameters in the register map.
0E20 0E21
[7:0] [7:0]
Reference inputs
Table 147. EEPROM Storage Sequence for Profile 0 and Profile 1 Settings
Address 0E22 Bits [7:0] Bit Name Profile 0 and Profile 1 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0600. Note that Register 0E23 and Register 0E24 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0600). The controller stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0600) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 0 and Profile 1 parameters in the register map.
0E23 0E24
[7:0] [7:0]
Profile 0 and Profile 1
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Table 148. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings
Address 0E25 Bits [7:0] Bit Name Profile 2 and Profile 3 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0680. Note that Register 0E26 and Register 0E27 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0680). The controller stores 0x0680 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0680) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 2 and Profile 3 parameters in the register map.
0E26 0E27
[7:0] [7:0]
Profile 2 and Profile 3
Table 149. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings
Address 0E28 Bits [7:0] Bit Name Profile 4 and Profile 5 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0700. Note that Register 0E29 and Register 0E2A are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0700). The controller stores 0x0700 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0700) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 4 and Profile 5 parameters in the register map.
0E29 0E2A
[7:0] [7:0]
Profile 4 and Profile 5
Table 150. EEPROM Storage Sequence for Profile 6 and Profile 7 Settings
Address 0E2B Bits [7:0] Bit Name Profile 6 and Profile 7 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0780. Note that Register 0E2C and Register 0E2C are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0780). The controller stores 0x0780 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0780) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 6 and Profile 7 parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
0E2C 0E2D
[7:0] [7:0]
Profile 6 and Profile 7
0E2E
[7:0]
I/O update
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Table 151. EEPROM Storage Sequence for Operational Control Settings
Address 0E2F Bits [7:0] Bit Name Operational controls Description The default value of this register is 0x10, which the controller interprets as a data instruction. Its decimal value is 16, which this tells the controller to transfer 17 bytes of data (16 + 1) beginning at the address specified by the next two bytes. The controller stores 0x10 in the EEPROM and increments the EEPROM address pointer. The default value of these two registers is 0x0A00. Note that Register 0E30 and Register 0E31 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 17 bytes from the register map (beginning at Address 0x0A00) to the EEPROM and increments the EEPROM address pointer by 18 (17 data bytes and one checksum byte). The 17 bytes transferred correspond to the operational controls parameters in the register map. The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
0E30 0E31
[7:0] [7:0]
Operational controls
0E32
[7:0]
I/O update
Table 152. EEPROM Storage Sequence for End of Data
Address 0E33 Bits [7:0] Bit Name End of data Description The default value of this register is 0xFF, which the controller interprets as an end instruction. The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters an idle state. Note that, if this were a pause rather than an end instruction, the controller actions would be the same except that the controller would not reset the EEPROM address pointer.
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AD9548 POWER SUPPLY PARTITIONS
The AD9548 features multiple power supplies, and their power consumption varies with the AD9548 configuration. This section provides information about which power supplies can be grouped together and how the power consumption of each block varies with frequency. The numbers quoted here are for comparison only. Please refer to the Specifications section for exact numbers. With each group, bypass capacitors of 1 F in parallel with 10 F should be used. Upon applying power to the device, internal circuitry monitors the 1.8 V digital core supply and the 3.3 V digital I/O supply. When these supplies cross the desired threshold level, the device generates an internal 10 s reset pulse. This pulse does not appear on the RESET pin. and the rest of the AVDD3 supply connections. Generally, these supply domains can be joined together. However, if an application requires 1.8 V CMOS driver operation in the clock distribution output block, then provide one 1.8 V supply domain to power the clock distribution output block. Each output driver has a dedicated supply pin, as shown in Table 153.
Table 153. Output Driver Supply Pins
Output Driver OUT0 OUT1 OUT2 OUT3 Supply Pin 31 37 38 44
1.8 V SUPPLIES
The 1.8 V supply domain consists of two main partitions, digital (DVDD) and analog (AVDD). These two supply domains must be kept separate.
3.3 V SUPPLIES
The 3.3 V supply domain consists of two main partitions, digital (DVDD3) and analog (AVDD3). Take care to keep these two supply domains separate. Furthermore, the AVDD3 consists of two subdomains: the clock distribution output domain (Pin 31, Pin 37, Pin 38, and Pin 44)
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AD9548 THERMAL PERFORMANCE
Table 154. Thermal Parameters for the AD9548 88-Lead LFCSP Package
Symbol JA JMA JMA JB JC JT
1 2
Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board1 Junction-to-ambient thermal resistance, 0.0 m/s airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/s airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/s airflow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-8 (moving air) Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air)
Value2 18 16 14 9 1.0 0.1
Unit C/W C/W C/W C/W C/W C/W
The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations.
The AD9548 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value as indicated in Table 154. PD is the power dissipation (see the Power Dissipation section).
Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first order approximation of TJ by the equation TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations.
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AD9548 CALCULATING DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients (, , , and (see Figure 40)) relate to the time constants (T1, T2, and T3) associated with the equivalent analog circuit for a third order loop filter (Figure 66).
FROM CHARGE PUMP R3 TO VCO
It can also be shown that the adjusted open-loop bandwidth leads to T2 (the secondary time constant of the second order loop filter) expressed as
T2 =
R2
C (T1 + T3 )
2
1
C1
C3 C2
08022-042
Calculation of the digital loop filter coefficients requires a scaling constant, K (related to the system clock frequency, fS), and the PLL feedback divide ratio, D.
K= 30,517,578,125 2 33 fS
Figure 66. Third Order Analog Loop Filter
The design process begins by deciding on two design parameters related to the second order loop filter shown in Figure 67: the desired open-loop bandwidth (fP) and phase margin ().
FROM CHARGE PUMP C1 TO VCO
D=S+
U +1 V
C2
08022-043
where S, U, and V are the integer and fractional feedback divider values that reside in the profile registers. Keep in mind that the desired integer feedback divide ratio is one more than the stored value of S (hence, the +1 term in the equation for D in this equation). This leads to the digital filter coefficients given by
R2
Figure 67. Second Order Analog Loop Filter
=
=
C 2 T2 D
T1 K
(1 + ( T ) )(1 + ( T ) )
2 2 C
An analysis of the second order loop filter leads to its primary time constant, T1. It can be shown that T1 is expressible in terms of fP and as
1 + ( C T2 )
1
C
3
2
- 32 1 1 + T T fS 1 2

T1 =
1 - sin( ) P cos( )
=
- 32 f S T1
where P = 2f P . An analysis of the third order loop filter leads to the definition of another time constant, T3. It can be shown that T3 is expressible in terms of the desired amount of additional attenuation introduced by R3 and C3 at some specified frequency offset (fOFFSET) from the PLL output frequency.
=
32 f S T3
Calculation of the coefficient register values requires the application of some special functions described as follows: The if() function y = if(test_statement, true_value, false_value) where test_statement is a conditional expression (for example, x < 3), true_value is what y equals if the conditional expression is true, and false_value is what y equals if the conditional expression is false. The round() function y = round(x)
T3 =
10
ATTEN 10
-1
OFFSET
where OFFSET = 2f OFFSET . Note that ATTEN is the desired excess attenuation in decibels. Furthermore, ATTEN and OFFSET should be chosen so that
T3
1 5 fP
With an expression for T1 and T3, it is possible to define an adjusted open-loop bandwidth (fC) that is slightly less than fP. It can be shown that C (fC expressed as a radian frequency) is expressible in terms of T1, T3, and (phase margin) as
C =
(T1 + T3 ) tan( ) 2 T1T3 + (T1 + T3 )
1+
[(T1 + T3 ) tan( )]
T1T3 + (T1 + T3 )
2 2
- 1
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AD9548
If x is an integer, then y = x. Otherwise, y is the nearest integer to x. For example, round(2.1) = 2, round(2.5) = 3, and round(-3.1) = -3. The ceil() function y = ceil(x) If x is an integer, then y = x. Otherwise, y is the next integer to the right on the number line. For example, ceil(2.8) = 3, whereas ceil(-2.8) = -2. The min() function y = min(x0, x1, ... xn) where x0 through xn is a list of real numbers, and the value of y is the number in the list that is the farthest to the left on the number line. The max() function y = max(x0, x1, ... xn) where x0 through xn is a list of real numbers, and the value of y is the number in the list that is the farthest to the right on the number line. The log2() function decimal point of 0 to the left to accommodate small values of . Calculation of 1 is a two-step process, as follows:
w = if ( < 1, - ceil(log 2 ( )), 0)
1 = if ( < 1, min[63, max(0, w)], 0)
If gain is necessary (that is, > 1), then it is beneficial to apply most or all of it to the front-end gain (2) implying that the calculation of 2 is to be done before 3. Calculation of 2 is a three-step process that leads directly to the calculation of 3.
x = if ( > 1, ceil(log 2 ( )), 0) y = if ( > 1, min[22, max(0, x)], 0)
2 = if ( y 8, 7, y )
3 = if ( y 8, y - 7, 0)
Calculation of 0 is a two-step process, as follows:
z = round( x 216+ 1 - 2 - 3 )
0 = min[65,535 , max(1, z )]
Using the example value of = 0.012735446 yields w = 6, so 1 = 6 x = 0 and y = 0, so 2 = 0 and 3 = 0 z = 53,416.332099584, so 0 = 53,416 This leads to the following quantized value, which is very close to the desired value of 0.012735446:
log 2 ( x) =
ln ( x) ln(2)
where ln() is the natural log function and x is a positive, nonzero number. Assume that the coefficient calculations for , , , and yield the following results:
= 0.012735446
= -6.98672 x 10 -5 = -7.50373 x 10 -5
quantized = 53416 x 2 -22 0.01273566821
CALCULATION OF THE REGISTER VALUES
The quantized coefficient consists of two components, 0 and 1 according to
= 0.002015399
These values are floating point numbers that must be quantized according to the bit widths of the linear and exponential components of the coefficients as they appear in the register map. Note that the calculations that follow indicate a positive value for the register entries of and . The reason is that and , which are supposed to be negative values, are stored in the AD9548 registers as positive values. The AD9548 converts the stored values to negative numbers within its signal processing core. A detailed description of the register value computations for , , , and is contained in the Calculation of the Register Values section to the Calculation of the Register Values section.
- quantized = 0 x 2 - (17 + 1 )
where 0 and 1 are the register values. Calculation of 1 is a twostep process that leads to the calculation of 0, which is also a twostep process.
x = -ceil(log 2 ( ))
1 = min[31, max(0, x)]
y = round( x 217 + 1 )
CALCULATION OF THE REGISTER VALUES
The quantized coefficient consists of four components, 0, 1, 2, and 3 according to
0 = min[131,071 , max(1, y )]
Using the example value of - = 6.98672 x 10-5 yields x = 13, so 1 = 13 y = 75,019.3347657728, so 0 = 75,019
quantized = 0 x 2
16- 1 + 2 + 3
where 0, 1, 2, and 3 are the register values. 2 provides frontend gain and 3 provides back-end gain, and 1 shifts the binary
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AD9548
This leads to the following quantized value, which is very close to the desired value of 6.98672x10-5:
CALCULATION OF THE REGISTER VALUES
The quantized coefficient consists of two components, 0 and 1, according to
quantized = 75,019 x 2 -30 6.986688823 x 10 -5
CALCULATION OF THE REGISTER VALUES
The quantized coefficient consists of two components, 0 and 1 according to
quantized = 0 x 2 - (15 +
1)
where 0 and 1 are the register values. Calculation of 1 is a two-step process that leads to the calculation of 0, which is also a two-step process.
- quantized = 0 x 2 - (17 + 1 )
where 0 and 1 are the register values. Calculation of 1 is a twostep process that leads to the calculation of 0, which is also a twostep process.
x = -ceil(log 2 ( ))
1 = min[31, max(0, x)]
y = round ( x 215 + 1 )
x = -ceil(log 2 ( ))
1 = min[31, max(0, x)]
y = round( x 217 + 1 )
0 = min[32,767 , max(1, y )]
Given the example value of = 0.002015399, the preceding formulas yield x = 8, 1 = 8 y = 16,906.392174592, 0 = 16,906 This leads to the following quantized value, which is very close to the desired value of 0.002015399:
0 = min[131,071 , max(1, y )]
Using the example value of - = 7.50373 x 10-5 yields x = 13, so 1 = 13 y = 80,570.6873700352, so 1 = 80,571 This leads to the following quantized value, which is very close to the desired value of 7.50373x10-5:
quantized = 16906 x 2 -23 0.0020153522 49
quantized = 80571 x 2 -30 7.503759116 x 10 -5
Rev. 0 | Page 109 of 112
AD9548 OUTLINE DIMENSIONS
12.00 BSC SQ 0.60 MAX 0.60 MAX
67 66 88 1
PIN 1 INDICATOR
PIN 1 INDICATOR 11.75 BSC SQ 0.50 BSC 6.15 6.00 SQ 5.85
EXPOSED PAD
0.50 0.40 0.30 TOP VIEW 0.70 0.65 0.60 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF
45 44 BOTTOM VIEW
23
22
0.90 0.85 0.80 SEATING PLANE
12 MAX
10.50 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VRRD.
Figure 68. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12 mm x 12 mm Body, Very Thin Quad (CP-88-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9548BCPZ 1 AD9548BCPZ-REEL71 AD9548/PCBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-88-2 CP-88-2 CP-88-2
Z = RoHS Compliant Part.
Rev. 0 | Page 110 of 112
032209-A
AD9548 NOTES
Rev. 0 | Page 111 of 112
AD9548 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08022-0-5/09(0)
Rev. 0 | Page 112 of 112

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